KR970003028B1 - A synchronizing circuit of tv camera - Google Patents

Abstract

None.

Description

Synchronization circuit of television camera

1 is a block diagram showing a horizontal scanning synchronous circuit employing the synchronous circuit of the present invention;

2 is an explanatory diagram of a phase comparator operation;

3 is an operation timing diagram of FIG.

4 is a block diagram showing a synchronization circuit for vertical scanning;

5 is an operation timing diagram,

6 is a waveform diagram for each component of a composite signal.

* Explanation of symbols for main parts of the drawings

1: Phase comparator 2,12: One short circuit

3,4,6,7: flip-flop 5: NAND gate

8: NOR gate 10: Strobe generation circuit

11: sample hold circuit

마한 콤포지트 신호를 이용하여 텔레비전 카메라의 동작을 텔레비전 모니터 동작에 동기시키는 동기회로에 관한 것이다.The present invention provides various synchronization circuits.

A synchronization circuit for synchronizing the operation of a television camera with the operation of a television monitor using a Mahan composite signal.

When a system is constructed using a plurality of television cameras, such as a surveillance system using a surveillance camera, it is desired to synchronize the operations of each camera in order to process a plurality of images simultaneously.

Normally, the operation of a television camera is provided on the basis of a basic clock obtained from an oscillation source incorporated in each television camera, and each camera operates at its own timing unless the operation timing is specifically synchronized. Therefore, conventionally, the synchronization of each camera operation is achieved by providing a common synchronization circuit to each camera.

Fig. 6 is a waveform diagram of the composite signal CS for synchronizing the operation of the television camera, showing the case of the NTSC system.

The composite signal CS is externally input to the television camera, and includes a horizontal synchronous signal HSo, a vertical synchronous signal VSo, and an equivalent pulse EP. These horizontal synchronizing signals HSo, vertical synchronizing signals VSo, and equivalent pulses EP are arranged in a time series in a predetermined order, and the horizontal synchronizing signals HS and vertical are obtained by using differentiators and integrators. The synchronization signal VS is separated. In other words, the derivative signal CS is differentiated so as to detect the fall, thereby obtaining the horizontal synchronization signal HS, and at the same time, the composite signal CS is differentiated, and the vertical synchronization signal VS is obtained at the change of the integral value.

The horizontal synchronizing signal HS and the vertical synchronizing signal VS obtained by separating from the composite signal CS are used for the reset signal for initial setting of the horizontal scan and the vertical scan, respectively, or the horizontal synchronizing signal HS created inside the television camera. _It is used for the reference signal of the PLL circuit which controls the phase of ₁ ), and the operation | movement of a television camera is synchronized with a composite signal.

However, according to the synchronous circuit described above, it is necessary to fully consider the delay of these analog circuits because analog circuits such as differentiators and integrators are used to obtain the horizontal synchronous signal HS and the vertical synchronous signal VS separately from the composite signal. Become.

Since the delay amount in this analog circuit is temperature dependent, setting of each parameter of the analog circuit in consideration of the delay amount becomes very difficult.

In addition, when obtaining the horizontal synchronization signal (HS), in order to distinguish the equivalent pulse (EP) having a half cycle, the stove is erected using a counter operating in the unit of horizontal scanning period in accordance with the falling of the horizontal synchronization signal (HS). Although the equivalent pulse (EP) is removed in one cycle, the counter operation during the horizontal scanning period causes the generation of bit noise, so that the noise of the video signal may overlap.

Therefore, an object of the present invention is to stably isolate the synchronization signal without using an analog circuit, and to synchronize the operation of the television camera with this synchronization signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a first feature is to provide a composite signal including various synchronization signals to a television camera equipped with an image pickup device that is scanned in the horizontal and vertical directions, and to operate the television camera at a predetermined timing. A synchronization circuit of a television camera for synchronizing, comprising: means for oscillating a basic clock inside the television camera, a horizontal synchronizing signal for determining a horizontal scanning timing of the image pickup device, and a horizontal scanning signal synchronized with a horizontal synchronizing signal as the basic clock; Means for producing, means for comparing the phase of the horizontal synchronization signal with the phase of the composite signal, and controlling oscillation of the basic clock according to the comparison output; timing of rising or falling of the composite signal is the horizontal scanning signal. The horizontal synchronization signal and the composite signal when Means for controlling the oscillation of the basic clock to synchronize the composite signal with the horizontal synchronization signal by stopping the phase comparison.

The second feature is to provide a composite signal in which the horizontal synchronization signal and the vertical synchronization signal are arranged in time series to a television camera equipped with an image pickup device that is scanned in the horizontal and vertical directions, and to operate the television camera at a predetermined timing. Means for receiving the composite signal by setting a strobe at a timing delayed by a predetermined period with respect to the falling timing of the composite signal in the synchronizing circuit of the synchronizing television camera, and means for generating a reset pulse at the falling timing of the signal received by the means. And means for setting a blanking period of vertical scanning of the image pickup device based on an output of a counter operating in units of horizontal scanning periods initially set in the reset pulse, and separating vertical synchronization signals from the composite signal. To control the vertical scanning timing of the image pickup device. There.

According to the present invention, a composite signal given to a television camera can receive a horizontal synchronizing signal or a vertical synchronizing signal without using an analog circuit such as a differentiator or integrator having a relatively large temperature characteristic, and ventilate the operation of the television camera to the composite signal. Stable operation can be obtained against temperature changes or fluctuations in power supply potential.

In addition, when the horizontal synchronization signal in the television camera is synchronized with the composite signal, a counter operating within the horizontal scanning period is unnecessary, and bit noise is not superimposed on the horizontal scanning period of the video signal.

Embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a block showing the synchronizing circuit of a television camera using the synchronizing circuit of the present invention, and shows the case of performing horizontal synchronizing.

In this figure, CS is a composite signal input from the outside of a television camera, CK is a basic clock having an oscillation source inside the television camera, and HS ₁ and HD ₁ are horizontal synchronous signals created from a basic clock CK and horizontal. It is a scanning signal.

The composite signal CS is input to the phase comparator 1 to compare the phase with the horizontal synchronization signal HS ₁ , and a voltage controlled oscillator constituting a phase locked loop (PLL) circuit by the comparison output OC. Oscillation frequency is controlled.

That is, this VCO generates the basic clock CK, and the horizontal synchronization signal HS created as the basic clock CK by controlling the oscillation of the basic clock CK according to the output OC of the phase comparator 1 ₁ ) is controlled to synchronize with the composite signal CS.

The composite signal CS is input to the one-shot circuit 2, and a one-shot signal OS having a timing pulse in its falling timing is created.

)가 타이밍신호로서 플립플롭(3,4)의 T입력에 부여된다. 둘의 플립플롭(3,4)은 원쇼트신호(OS)에 따라 동작하는 2비트의 시프레지스터를 구성하는 것으로, 플립플롭(3)의 D입력에 수평주사신호(HD₁)가 부여됨과 동시에 플립플롭(3)의 Q출력이 플립플롭(4)의 D 입력에 부여되고 있다.This one short signal OS is an inverted signal thereof.

Is applied to the T input of the flip-flops 3 and 4 as a timing signal. The two flip-flops 3 and 4 constitute a 2-bit sequencer that operates according to the one short signal OS, and the horizontal scan signal HD ₁ is applied to the D input of the flip-flop 3. The Q output of the flip flop 3 is provided to the D input of the flip flop 4.

출력이 NAND 게이트(5)의 입력에 부여되고, 이 NAND 게이트(5)의 출력이 다음단의 플립플롭(6)의 D 압력에 부여된다. 이 플립플롭(6)은 플립플롭(7)과 함께 기본클록(CK)에 따라 동작하는 2비트의 시프트레지스터를 구성하고 있으며, 각 플립플롭(6,7)의 T 입력에는 기본클록(CK)이 부여된다.Then, the Q output of the flip-flop 3 and the flip-flop 4

The output is applied to the input of the NAND gate 5, and the output of this NAND gate 5 is applied to the D pressure of the flip-flop 6 of the next stage. The flip-flop 6 constitutes a 2-bit shift register that operates in accordance with the basic clock CK together with the flip-flop 7. The flip-flop 6 has a basic clock CK at the T input of each flip-flop 6, 7. Is given.

출력이 NOR 게이트(8)의 입력에 부여되고, 이 NOR게이트(8)의 출력이 콘트롤신호(C)로서 위상비교기(1)에 부여된다.Then, the Q output of the flip-flop 6 and the flip-flop 7

An output is applied to the input of the NOR gate 8, and the output of this NOR gate 8 is supplied to the phase comparator 1 as a control signal C.

FIG. 2 illustrates the operation of the phase comparator 1. FIG. 2A is a diagram showing each input / output terminal, and FIG.

The phase comparator 1 compares the falling timings of both input signals 1 ₁ and 1 ₂ , for example, compares the falling timings of the input signals 11, for example, the falling of the input signals 1 ₁ is an input signal. ₍₁₂₎ the output of is when more fast timing descent (OC) is the "H" (high level), as opposed to when the later timing than the fall of the input signal ₍₁₁₎ is input signal ₍₁₂₎ falling in the The output OC is configured to be "L", and this comparison operation is controlled by the control signal C.

That is, when the control signal C is "1", the comparison operation is stopped, and the output 0C is fixed to "M" (middle level). When the controller signal C is "0" and the output OC is "M", when the input signal 1 ₁ falls first, the output OC becomes "H" until the rising of the input signal 1 ₂ , and vice versa. the input signal ₍₁₂₎ is the output (OC) is "L" until the fall of the signal if the input ₍₁₂₎ before falling.

In the remaining period, the output OC is fixed at " M ".

The output OC is used to control the VCO to create the basic clock CK. When the output OC becomes "H", the frequency is higher than the predetermined value. When the output OC is "L", the frequency is lower than the predetermined value. At the same time, the waveguide is set to a predetermined value at " M ".

Therefore, when the horizontal synchronizing signal HS ₁ becomes faster or later with respect to the composite signal CS, the basic clock frequency CK, which is the reference for the horizontal synchronizing signal HS ₁ , becomes lower or higher by a predetermined period so that the horizontal synchronizing signal HS ₁ becomes horizontal. The signal HS ₁ is synchronized with the composite signal CS.

Next, the comparison operation stop of the phase comparator 1 will be described.

FIG. 3 is a timing diagram showing the operation of FIG.

출력이 「0」가되고, NAND 게이트(5)의 출력이「1」이된다.When the horizontal synchronization signal HS is not synchronized with the composite signal CS (FIG. 3 (a)), the Q output of the flip-flop 3 becomes "1" at each timing of the one short signal OS. At the same time

The output becomes "0" and the output of the NAND gate 5 becomes "1".

출력이「0」가되고, NOR 게이트(8)출력이「0」이된다.Then, the Q output of the flip-flop 6 becomes "1" and the flip-flop 7

The output becomes "0" and the NOR gate 8 output becomes "0".

Therefore, the control signal becomes " 0 " so that the phase comparator 1 compares the phase between the horizontal synchronization signal HD ₁ and the composite signal CS.

Here, when the horizontal synchronization signal HS ₁ coincides with the equivalent pulse EP having different synchronizations as in the timing t ₁ of FIG. 3 (a), the Q output of the flip-flop 3 is once " 0 " The output of the NAND gate 5 is "1" human body, and the comparison operation of the phase comparator 1 is not stopped.

출력이「1」이되는 점에서 NAND 게이트(5) 출력이 일단「0」이되어 플립플롭(6)의 출력을「0」으로 하고, NOR 게이트(8)의 출력, 즉 콘트롤신호(C)를 「1」로 하여 위상비교기(1)의 비교동작을 정지하기 때문에 등가펄스(EP) 및 수직동기신호(VSo)의 기간에서 PLL 회로가 잠긴 상태가 되는 경우도 있으나 수평동기신호(HSo) 기간에 수평동기신호(HS₁)가 콤포지트신호(CS)에 동기되어 있지 않으면 PLL 회로는 잠긴상태가 해제된다.In such a case, when the Q output of the flip-flop 3 becomes "1" at the next timing t ₂ , the flip-flop 6 is turned off.

At the point where the output becomes "1", the output of the NAND gate 5 becomes "0" once, and the output of the flip-flop 6 is "0", and the output of the NOR gate 8, that is, the control signal C Since the comparison operation of the phase comparator 1 is stopped by setting " 1 ", the PLL circuit may be locked in the period of the equivalent pulse EP and the vertical synchronization signal VSo, but the horizontal synchronization signal HSo period If the horizontal synchronizing signal HS ₁ is not synchronized with the composite signal CS, the locked state of the PLL circuit is released.

출력이「1」이되고, NAND 게이트(5)의 출력이「1」이된다.Next, when the horizontal synchronizing signal HS is substantially synchronized with the composite signal CS (FIG. 3B), the Q output of the flip-flop 3 at each timing of the one short signal OS is " 0 "and the flip-flop 4

The output becomes "1", and the output of the NAND gate 5 becomes "1".

Then, the flip-flops 6 and 7 and the NOR gate 8 operate as in the case of FIG. 3 (a) to operate the phase comparator 1.

출력이「0」인 사실로 인하여 NOR 게이트(8)의 출력이「1」이되어 위상비교기(1)의 비교동작이 정지된다. 그리고, 다음 타이밍(t₂)에서 플립플롭(3)의Q 출력이「0」이되면 NAND 게이트(5)의 출력이 재차「1」이되어 플립플롭(6)의 Q 출력을「1」로 하고, NOR 게이트(8)의 출력을「0」으로하여 위상비교기(1)를 재차 동작시킨다.Therefore, when the equivalent pulse EP is input as in the timing t ₁ of FIG. 3 (b), the Q output of the pull-flop 3 becomes "1", and the output of the NAND gate 5 is set to "0". do. At this time, the flip-flop 7

Due to the fact that the output is "0", the output of the NOR gate 8 becomes "1" and the comparison operation of the phase comparator 1 is stopped. When the Q output of the flip-flop 3 becomes "0" at the next timing t ₂ , the output of the NAND gate 5 becomes "1" again, and the Q output of the flip-flop 6 becomes "1". Then, the phase comparator 1 is operated again with the output of the NOR gate 8 as "0".

Therefore, in the period of equivalent pulse EP and vertical synchronization signal VS _{0 in} which the period is half of the horizontal synchronization signal HS ₀ , the comparison operation of the phase comparator 1 is stopped and started every cycle. Each pulse between the equivalent pulse EP and the vertical synchronization signal VS ₀ is ignored at intervals of one cycle, and the horizontal synchronization signal HS ₀ is separated from the composite signal CS.

4 is a flip-flop diagram of a synchronous circuit for vertical synchronization of a television camera, and FIG. 5 is a timing diagram.

The strobe circuit 10 prepares the strobe signal SS which raises a strobe at a timing which is delayed for a certain period with respect to the fall timing of the composite signal CS, and is applied to the sample hold circuit 11.

The period in which the strobe signal SS is delayed with respect to the fall of the composite signal CS is given by using a counter operating within the blanking period of horizontal scanning or a delay circuit having a short delay time, and the fall of the composite signal CS. Is set to a period including a period from rising to rising (except for the period of the vertical synchronization signal VS ₀ ).

The composite signal CS becomes " 0 " at each timing of the strobe signal SS in the vertical synchronization signal VS ₀ period, and becomes " 1 " at each timing of the strobe signal SS in the other period. The synchronization signal VS is separated.

That is, the vertical synchronizing signal VS is obtained at the output of the sample hold circuit 11 and descends at the pulse A of FIG. 5 and rises at the subsequent pulse B. FIG.

In this way, the vertical synchronization signal VS separated from the composite signal CS is input to the one-shot circuit 12, and its falling timing is detected so that the vertical reset signal VR is obtained. The vertical reset signal VR initializes the counter 13 for setting the blanking period of the vertical scan, and is configured to synchronize the vertical scan signal VD.

The counter 13 counts the horizontal scanning player (horizontal scanning signal HD), sets the end of the blanking period at the timing when the count value CV reaches a predetermined value, and stops the counting operation. Accordingly, the vertical scan signal VD generated based on the count value CV of the counter 13 is synchronized with the composite signal, and the blanking period is set by the counter 13 for a predetermined period, for example, the horizontal scan period 1H. It is set to 9 cycles (9H).

Further, the vertical reset signal VR outputs the horizontal blanking signal HB applied to the T input of the flip-flop 14 for obtaining the field identification signal HLD at each timing.

Since one field is normally 262.5H (NTSC system), the horizontal blanking signal HB repeats "1" and "0" alternately at the reset timing for each field. Therefore, the field identification signal FLD obtained at the Q output of the flip-flop 14 shows, for example, "1" in the even field and "0" in the odd field.

According to the present invention, since the horizontal synchronization signal and the vertical synchronization signal can be separated from the composite signal provided to the television camera without using an analog circuit, synchronization can be performed together with the driving circuit of the image pickup device composed of a digital circuit. It can be reduced to one chip and is effective for reducing the size and weight of a television camera.

In addition, the counter that does not need to be operated during the horizontal scanning period is eliminated, and the operation of the synchronization circuit is stabilized in that the overlap of the bit noise in the video signal is prevented and the variation of the operating characteristics due to the temperature change is very small. Improvement is expected.

Claims (1)

A synchronizing circuit of a television camera for providing a composite signal including various synchronizing signals to a television camera equipped with an image pickup device that scans in the horizontal and vertical directions and synchronizing the operation of the television camera at a predetermined timing. Means for oscillating a clock, means for generating a horizontal synchronizing signal for determining a horizontal scanning timing of the image pickup device, and a horizontal scanning signal synchronized with the horizontal synchronizing signal as the basic clock, and a phase of the composite synchronizing signal for Means for controlling the oscillation of the basic clock according to the comparison output at the same time as the phase, and when the rising or falling timing of the composite signal is within a predetermined period of the horizontal scanning signal, the horizontal synchronizing signal and the composite signal Means for fixing the comparison output by stopping phase comparison As provided, and synchronization circuit of a television camera, characterized in that for controlling the oscillation of the fundamental clock is the composite signal and the horizontal synchronization signal is in synchronization.

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