JPH0837609A - Pedestal clamp device for composite signal - Google Patents

Abstract

PURPOSE:To logically produce a clamp circuit by means of a MOS to prevent the oscillation and to improve the clamping accuracy. CONSTITUTION:A pedestal clamping operation is carried out for a composite signal in time sharing and in each single direction. For instance, only a driver 4A is activated and biased in the higher voltage direction by a comparator 2 in the first period A. Then only a driver 4B is activated and biased in the lower voltage direction in a period B that starts after a fixed time. Thus the composite signal is clamped by a driver of the higher driving capability and then by a driver of the lower driving capability when the signal undergoes a pedestal clamping operation in time sharing and in each single direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pedestal clamp device for composite signals reproduced from a home video tape recorder (VTR) or a general television.

[0002]

2. Description of the Related Art For a signal called a composite signal reproduced from a VTR or a general television, for example, the magnitude of the signal is usually regulated, but the absolute value of the voltage level is not regulated. Therefore, in order to extract the part containing video information from the composite signal and use it in the system, it is necessary to bias a certain point of the input signal to a certain fixed voltage (pedestal level). It is called a clamp.

FIG. 8 is a schematic view of a conventional pedestal clamp device, which is clamped by a capacitor 1, a comparator 2 with negative feedback, and a pair of drivers 3A, 3B in which one of them is always active. The circuit is configured. Reference numeral 5 is an input portion, 6 is an output portion, and Vref is a reference voltage of the comparator 2. When the composite signal is input to the input unit 5 and a part of the composite signal to be pedestal clamped is detected, the comparator 2
9, the clamp operation is started, and when the input signal is lower than the clamp voltage as shown in FIG. 9, the driver 2A is driven by the comparator 2 and the voltage level of the input signal is controlled to increase, and the control is performed. Therefore, when the input signal becomes higher than the clamp voltage, the driver 2B is driven by the comparator 2 and the voltage level of the input signal is controlled to decrease. By such control, the voltage of the portion of the composite signal where the pedestal clamp is performed is biased to the pedestal level.

[0004]

However, in the conventional pedestal clamp device, the portion of the composite signal to be clamped is the comparator 2 and the two drivers 3.
Since the clamp circuit consisting of A and 3B is used to bias the comparator 2 by applying negative feedback, the pedestal-clamped signal output from the output unit 6 easily oscillates, as shown in FIG. That is, when the input signal from the input unit 5 is lower than the clamp voltage during the pedestal clamp, the input signal is biased in the positive direction until reaching the clamp voltage, and conversely, when the input signal is higher than the clamp voltage. Has a negative bias. Therefore, during the pedestal clamp period,
There is a possibility of oscillation between the positive biased state and the negative biased state.

In order to prevent such oscillation, the time constant of the clamp circuit composed of the comparator 2 and the drivers 3A and 3B may be adjusted, but if the comparator 2 with negative feedback is made by MOS, the circuit will be There are complex issues. Also, a driver with a large drive capacity can change the output in an extremely short time,
Since the overrun is large, the clamping accuracy is not always good. Therefore, a first object of the present invention is to provide a pedestal clamp device for composite signals in which a clamp circuit which prevents oscillation can be made logically by MOS. A second object is to provide a pedestal clamp device for composite signals, which can improve the clamping accuracy.

[0006]

The invention according to claim 1 is characterized in that the pedestal clamp in the composite signal is time-divisionally performed in each single direction. The invention of claim 2 is characterized in that, when performing pedestal clamping in a composite signal in a time division manner and in each single direction, the pedestal clamping is performed by a driver having a large driving ability and then a driver having a small driving ability.

[0007]

Since the pedestal clamp is time-divided and the pedestal clamp is performed in each single direction, a clamp circuit that does not oscillate can be logically manufactured by MOS. Also, by first clamping with a driver having a large drive capacity, large and rough clamping is performed, and then by using a driver with a small drive capacity, accurate clamping can be performed.

[0008]

Embodiments of the present invention will be described below. FIG. 1 is a schematic view of a pedestal clamp device according to an embodiment of the present invention. Reference numeral 1 is a capacitor, and a composite signal is input through the input unit 5. Reference numeral 2 is a comparator, which compares the output of the capacitor 1 with the reference voltage Vref. Reference numerals 4A and 4B denote drivers, and the periods in which the drivers 4A and 4B are enabled are divided so that the pedestal clamp can be time-divisionally performed in each single direction. That is, one driver 4A is enabled only for a certain period A, and the other driver 4B is enabled only for a period B started after the period A has elapsed. A clamp circuit is composed of the comparator 2 and the drivers 4A and 4B. 6 is an output unit.

FIG. 2 is a waveform diagram of the pedestal clamped output signal obtained by the pedestal clamp device of FIG. 1, in which only one driver 4A is active during period A and the input signal is biased in the positive direction. There is. During the period B started after the passage of period A, only the other driver 4B is active and the input signal is biased in the reverse direction, that is, in the negative direction. In this way, the drivers 4A and 4A are completely divided into the A period and the B period.
Since B is separately enabled, the clamp circuit does not oscillate. Therefore, it is not necessary to adjust the time constant to prevent oscillation as in the conventional case, and a clamp circuit in which oscillation is prevented by MOS can be easily manufactured in terms of logic.

FIG. 3 shows an example in which the clamp circuit of FIG. 1 is logically constituted by MOS. 21 is an input unit, 2
2 is an output unit, 23 is a comparator, Vref is a reference voltage, 24A is one driver, 24B is the other driver, 25A and 25B are AND circuits, 26 is a line counter, 27 is a capacitor, and C is an internal clock input unit. is there. A composite signal is input to the input unit 21, and when a signal of a portion that performs pedestal clamping is input to the input unit 21, a drive signal is supplied to the comparator 23 and the comparator 23 is ready to be driven.

On the other hand, in the line counter 26, counting is started in conjunction with, for example, a drive signal to the comparator 23, and the first A period and the subsequent B period of the period during which the pedestal clamp is performed are predetermined depending on the count number. The internal clock input to C of the line counter 26 is used to switch between the A period and the B period. That is, in the period A, an ON signal is input from the line counter 26 to one AND circuit 25A, an OFF signal is input to the other AND circuit 25B, and one driver 24A operates according to the output signal of one AND circuit 25A. Pedestal clamp is performed. During this time, the other driver 24B does not operate. When the period A ends, the period B starts after a certain period of time. In the period B, the line counter 26 inputs an OFF signal to one AND circuit 25A and an ON signal to the other AND circuit 25B. The other driver 24B operates by the output signal of the other AND circuit 25B to perform pedestal clamping. During this time, one driver 24A does not operate. In this way, the pedestal clamp having the waveform as shown in FIG. 2 is performed.

The part of the composite signal that is pedestal clamped is not particularly limited, but in the example of FIG. 3, the pedestal clamp is performed during the equalization pulse of the composite signal. in this case,
When the composite signal is input to the input unit 21, the drive signal is supplied to the comparator 23 corresponding to the period of the equalization pulse, and the comparator 23 operates during that period.
The line counter 26 is built in a general VTR, detects the vertical synchronizing period of the composite signal, and increases the counter value by the horizontal synchronizing pulse (sync signal). Further, the internal clock is also built in a general VTR. Therefore, by using these line counters and the internal clock, the comparator 23 during the equalization pulse in the composite signal.
Drive signal can be generated.

Next, the operation of the line counter 26 will be specifically described with reference to FIG. 4. The vertical synchronizing period in the composite signal generally appears twice in one screen, but in a general VTR. When the built-in vertical synchronization period detection circuit detects this vertical synchronization period, the line counter 26 is reset to the initial state. The horizontal synchronizing pulse (sync signal) B appearing after the reset is counted by the line counter 26 to detect the period of the equalizing pulse. On the other hand, using the internal clock,
A period and B period in the period of the equalizing pulse are defined, and A
In the period, the ON signal is supplied only to the AND circuit 25A and the pedestal clamp is performed by the driver 24A, and in the subsequent period B, the ON signal is supplied only to the AND circuit 25B and the pedestal clamp is performed by the driver 24B.

FIG. 5 is a waveform diagram of a voltage of an output signal when a pedestal clamp is performed by switching between a driver having a large driving capability and a driver having a small driving capability by using a plurality of drivers having different driving capabilities. The output change by a driver with a large drive capacity is rapid and overrun is likely to occur, but if you switch to a driver with a smaller drive capacity and drive after that, the output change will be slower, but an overrun does not occur and accurate clamping is performed. You can The accuracy can be improved by about 1/10 as compared with the case where the same drive capacity is actually used. Note that FIG. 6 is a waveform diagram of the voltage of the output signal when the pedestal clamp is performed using the driver having the same drive capability, and it can be seen that the clamp accuracy is inferior as compared with FIG.

FIG. 7 shows an example in which a clamp circuit which operates to have the waveform shown in FIG. 5 is logically constructed by MOS. 24A is one driver with large drive capacity, 24B is the other driver with large drive capacity, 27A is one driver with small drive capacity,
27B is the other driver with small drive capacity, 25
A, 25B, 28A and 28B are AND circuits. In the line counter 26, for example, counting is started in synchronization with a drive signal to the comparator 23, and among the periods in which the pedestal clamp is performed, the first A period and the next B period in which the pedestal clamp is performed have a large drive capacity. The second A period and the next B period, which are determined and clamped with a small drive capacity, are predetermined, and the internal A clock input to C of the line counter 26 is used to set the first A period and the first A period. B period, second A
The period and the B period can be switched.

That is, in the first period A, the line counter 26 inputs the ON signal only to the AND circuit 25A,
The OFF signal is input to the other AND circuits 25B, 28A, 28B, and the driver 24A having a large drive capability operates according to the output signal of the AND circuit 25A to perform the pedestal clamp. During this time, the other drivers 24B, 27
A and 27B do not work. When this first A period ends, the first B period starts after a certain period of time,
During the period, the ON signal is input only from the line counter 26 to the AND circuit 25B, and the other AND circuits 25A and 28A
The OFF signal is input to A and 28B, and the driver 24B having a large drive capability is output by the output signal of the AND circuit 25B.
Operates and pedestal clamp is performed. During this time, the other drivers 24A, 27A and 27B do not operate. Next, when the second period A arrives, the ON signal is supplied only from the line counter 26 to the AND circuit 28A during this period, and only the driver 27A having a small drive capability operates by the output signal to perform the pedestal clamp. Then, when the second B period arrives, the ON signal is supplied only from the line counter 26 to the AND circuit 28B during this period, and only the driver 27B having a small driving capability operates by the output signal to perform the pedestal clamp. In this way, the pedestal clamp having the waveform as shown in FIG. 5 is performed.

Although the embodiments of the present invention have been described above, the present invention is not particularly limited to the portion of the pedestal clamp in the composite signal. Therefore, the detecting means and the clamping means for the period during which the pedestal clamp is performed are not particularly limited.

[0018]

According to the first aspect of the present invention, a clamp circuit that does not oscillate can be easily manufactured in terms of logic using MOS. According to the invention of claim 2, the accuracy of the clamp can be improved.

[Brief description of drawings]

FIG. 1 is a schematic view of a pedestal clamp device according to an embodiment of the present invention.

FIG. 2 is a waveform diagram of the voltage of the output signal controlled by the pedestal clamp device according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example in which a clamp circuit in a pedestal clamp device according to an embodiment of the present invention is logically configured by MOS.

FIG. 4 is an explanatory diagram of a line counter shown in FIG.

FIG. 5 is a voltage waveform diagram of an output signal controlled by a pedestal clamp device according to another embodiment of the present invention.

FIG. 6 is a waveform diagram of a voltage of an output signal when drivers having the same drive capability are used.

FIG. 7 is a circuit diagram showing an example in which a clamp circuit in a pedestal clamp device according to another embodiment of the present invention is logically configured by MOS.

FIG. 8 is a schematic view of a conventional pedestal clamp device.

FIG. 9 is a waveform diagram of a voltage of an output signal controlled by a conventional pedestal clamp device.

[Explanation of symbols]

1, 27 capacitors 2, 23 comparators 3A, 3B, 4A, 4B, 24A, 24B, 27A, 2
7B driver 25A, 25B, 28A, 28B AND circuit 26 line counter 5,21 input section 6,22 output section

Claims (2)

[Claims] 1. A pedestal clamp device for a composite signal, wherein the pedestal clamp for the composite signal is time-divisionally performed in each single direction. 2. A pedestal for a composite signal, characterized in that, when pedestal clamping of a composite signal is performed in a time-division manner and in each direction, the pedestal is clamped by a driver having a large drive capacity and then by a driver having a small drive capacity. Clamp device.