JPH0675547A - Display device - Google Patents

Abstract

PURPOSE:To obtain a display device having the optimum and the shortest video cut-off time depending on conditions before and after switching of a input synchronizing signal. CONSTITUTION:Horizontal and vertical synchronizing signals are respectively inputted to input terminals T1 and T2 of a CPU 1, by counting frequency values of this horizontal and vertical synchronizing signals and always holding them, an output terminal T3 of the CPU 1 is made non-active when counted values counted every prescribed time coincides with a counted value of the last time, or the output terminal T3 of the CPU 1 enters the active state during a time corresponding to difference of counted values when the counted value does not coincide with the counted value of the last time. Therefore, when an input terminal T4 of a video cut-off circuit 2 enters the active state, an output terminal T5 also enters the active state, and since an input terminal T7 of a video output circuit 3 enters the active state, the transmission of a video output signal supplied to an input terminal T6 of the video output circuit 3 to an output terminal T8 is cut-off, and a picture is not displayed in a video output device 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device which controls a video cutoff time when an input synchronizing signal is switched by using a CPU.

[0002]

2. Description of the Related Art Conventionally (not shown), in a display device capable of receiving a plurality of different horizontal and vertical synchronizing signals, when the input synchronizing signal is switched, the oscillation and deflection circuits inside the display device are switched. It took time to correspond to the synchronization frequency, and during that time, the video was in synchronization.

Therefore, the following two methods are considered and the video signal is temporarily cut off.

The first is to compare the phase of the synchronization signal before switching and that after switching to determine whether or not the input synchronization signal has been switched.

Secondly, the synchronizing frequency measured by the CPU is determined by a method of comparing before and after switching, and when the input synchronizing signal is switched, the image is cut off only for a predetermined time. is there.

[0006]

As described above, the conventional display device has a method of cutting off the image only for a predetermined time when the input synchronizing signal is switched, but that time can be assumed by the display device. It was set for the longest time.

However, the unstable state of the internal circuit of such a display device, that is, the time during which the synchronization is flowing depends on the frequency difference of the synchronization signal before and after the switching, and if there is no difference, the state is unstable. Time will be shorter.

Therefore, since the video cutoff time at the time of switching the input synchronizing signal is constant, the operator is always kept in the cutoff state for all the switching conditions for a predetermined time and waits until the video is output. There was an inconvenience.

Therefore, it is an object of the present invention to provide a display device which obtains an optimum and shortest video cutoff time depending on the conditions before and after the switching of the input synchronizing signal.

[0010]

According to a first aspect of the present invention, a display device has a CPU for controlling a video output signal with respect to a plurality of different horizontal and vertical synchronizing signals, and the video output signal based on a command from the CPU. In a display device having an image cutoff circuit for cutting off, the CPU counts a preset time for each preset frequency value difference due to the frequency value difference between before and after switching of the frequencies of the horizontal and vertical synchronizing signals. The video cutoff circuit cuts off the video output signal based on the counted result.

A display device according to a second aspect of the present invention includes horizontal and vertical frequency / voltage converters for converting DC voltages proportional to the frequencies of the horizontal and vertical synchronizing signals, respectively, and is provided for converting the frequency of the horizontal and vertical synchronizing signals. Due to the difference between the frequency values before and after the switching and the difference between the DC voltage values output from the horizontal and vertical frequency / voltage converters, the preset time for the difference between the DC voltage values set in advance is set in the CP.
It is characterized by counting with U.

[0012]

FIG. 1 is a block diagram showing an embodiment of the first invention, which is a CPU for controlling a video output signal for a plurality of different horizontal and vertical synchronizing signals of a display device.
1. A video cutoff circuit 2 which cuts off a video output signal based on a command from the CPU 1. A video cutoff circuit 2 which cuts a video output signal
Is a display device including a video output circuit 3 which is sent to the video output device 4 under the control of, and a video output device 4 which displays an image by a video output signal of the video output circuit 3.

Here, an embodiment of the first invention will be described.
The operation will be described.

First, a horizontal synchronizing signal is input to the input terminal T1 of the CPU 1 and a vertical synchronizing signal is input to the input terminal T2, and the frequency values of the horizontal and vertical synchronizing signals are counted and held at all times, thereby maintaining a certain level. If the count value counted for each period matches the previous count value, the output terminal T3 of the CPU1 is held inactive, and if the count value does not match the previous count value, the output terminal T3 of the CPU1 counts. The time corresponding to the difference (long when the difference is large, short when the difference is small) is activated.

Therefore, the input terminal T4 of the video cutoff circuit 2 connected to the output terminal T3 of the CPU 1 becomes active, and the output terminal T5 also becomes active, so that the input terminal T7 of the video output circuit 3 becomes active. Therefore, the video output signal supplied to the input terminal T6 of the video output circuit 3 is cut off, the video output signal is not sent from the output terminal T8 of the video output circuit 3, and the video output device 4 does not display an image.

If the input terminal T7 is in the non-active state, the video output signal supplied to the input terminal T6 is output through the output terminal T8 to the input terminal T of the video output device 4.
9 and the image is displayed on the video output device 4.

Next, FIG. 2 is a block diagram showing an embodiment of the second invention. The difference in the configuration from the embodiment of the first invention is proportional to the frequencies of the horizontal and vertical synchronizing signals. A horizontal / vertical frequency / voltage converter of analog / digital converter (hereinafter referred to as F / V converter) F / V converters 105 and 106 for converting each to a DC voltage by providing CP
It is controlled by U101, and the following is the same as the one embodiment of the first invention.

Therefore, regarding one embodiment of the second invention,
The operation will be described.

In the second embodiment of the present invention, horizontal and vertical synchronizing signals are input to input terminals T110 and T111 of F / V converters 105 and 106 to generate a DC voltage proportional to the frequencies of the horizontal and vertical synchronizing signals. F / V converted respectively
Output terminals T112 and T11 of converters 105 and 106
3 is sent.

The converted DC voltage is applied to the CPU 10
1 counts the DC voltage value through the input terminals T101 and 102 and always holds the DC voltage value, so that when the count value counted at a certain fixed period matches the previous count value, the output terminal T103 of the CPU 101 is turned off. If the count value is held active and does not match the previous count value, the output terminal T of the CPU 101
The following is the same as that of the first embodiment of the present invention, where 103 is set to an active state for a time corresponding to the difference in the count value (long when the difference is large, short when the difference is small).

[0021]

As described above, according to the display device of the present invention, when switching the frequencies of a plurality of different horizontal and vertical sync signals, the optimum and shortest video cutoff time can be obtained, thereby eliminating unnecessary video cutoff. This has the effects of reducing time and improving convenience.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a first invention.

FIG. 2 is a block diagram of an embodiment of the second invention.

[Explanation of symbols]

1, 101 CPU 2 Video cutoff circuit 3 Video output circuit 4 Display device (video output device) 105 Horizontal frequency / voltage converter (F / V converter) 106 Vertical frequency / voltage converter (F / V converter) T1, T2 T101, T102 CPU (input terminal) T3, T103 CPU (output terminal) T4 video cutoff circuit (input terminal) T6, T7 video output circuit (input terminal) T8 video output circuit (output terminal) T9 display device (input terminal) T110 , T111 Horizontal and vertical frequency / voltage converter (input terminal) T112, T113 Horizontal and vertical frequency / voltage converter (output terminal)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H04N 5/66 Z 9068-5C

Claims (2)

[Claims] 1. A display device having a CPU for controlling a video output signal for a plurality of different horizontal and vertical synchronizing signals, and a video blocking circuit for blocking the video output signal based on a command from the CPU. Based on the difference between the frequency values of the horizontal and vertical synchronizing signals before and after switching, the CPU counts the preset time for each preset frequency value difference, and based on the counted result, the above-mentioned image is displayed. A display device, wherein a cutoff circuit cuts off the video output signal. 2. A horizontal and vertical frequency / voltage converter for converting into a DC voltage proportional to the frequency of the horizontal and vertical synchronizing signals, respectively, and is provided before and after switching of the frequencies of the horizontal and vertical synchronizing signals. The difference between the DC voltage values output from the horizontal and vertical frequency / voltage converters according to the frequency value difference, and the CPU counts a preset time for each preset DC voltage value difference. The display device according to claim 1.