JPH07222024A - Image display device having vertical amplitude stabilizing circuit - Google Patents

Image display device having vertical amplitude stabilizing circuit

Info

Publication number
JPH07222024A
JPH07222024A JP910394A JP910394A JPH07222024A JP H07222024 A JPH07222024 A JP H07222024A JP 910394 A JP910394 A JP 910394A JP 910394 A JP910394 A JP 910394A JP H07222024 A JPH07222024 A JP H07222024A
Authority
JP
Japan
Prior art keywords
circuit
vertical
voltage
frequency
vertical amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP910394A
Other languages
Japanese (ja)
Inventor
Yuji Nagayoshi
祐二 永吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Image Information Systems Inc
Hitachi Ltd
Hitachi Advanced Digital Inc
Original Assignee
Hitachi Image Information Systems Inc
Hitachi Ltd
Hitachi Video and Information System Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Image Information Systems Inc, Hitachi Ltd, Hitachi Video and Information System Inc filed Critical Hitachi Image Information Systems Inc
Priority to JP910394A priority Critical patent/JPH07222024A/en
Publication of JPH07222024A publication Critical patent/JPH07222024A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate vertical size fluctuation due to noise or the like and to reduce a time till the vertical size at signal changeover is made stable. CONSTITUTION:The image display device is provided with a frequency /voltage conversion circuit 301 generating a voltage in response to a vertical synchronizing signal with a different frequency and a vertical amplitude stabilizing circuit 306 having plural integration circuits 302, 303 whose time constant is different to make the fluctuation of an output voltage of the circuit 301 stable, a buffer circuit 305 connecting outputs of the circuits 302, 303 to a vertical amplitude control circuit, a switching means 304 selecting either of the integration circuits, and a control circuit 308 controlling the operating time.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、マルチスキャンディス
プレイのように異なる周波数の垂直同期信号を入力とし
て動作するディスプレイ装置の垂直振幅安定化回路に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical amplitude stabilizing circuit for a display device such as a multi-scan display which operates by inputting vertical synchronizing signals of different frequencies.

【0002】[0002]

【従来の技術】図3にマルチスキャンディスプレイのブ
ロック図を示し、図4に図3の垂直励振回路周辺ブロッ
ク図を示す。また図4における垂直振幅安定化回路の従
来技術を図5に示す。
2. Description of the Related Art FIG. 3 shows a block diagram of a multi-scan display, and FIG. 4 shows a block diagram around a vertical excitation circuit shown in FIG. FIG. 5 shows a conventional technique of the vertical amplitude stabilizing circuit in FIG.

【0003】図5において、周波数・電圧変換回路1は
図7に示すように入力された垂直同期信号の周波数に応
じた電圧を出力する。この出力電圧がノイズ等により不
安定になると垂直サイズが変動する。
In FIG. 5, the frequency / voltage conversion circuit 1 outputs a voltage according to the frequency of the input vertical synchronizing signal as shown in FIG. If this output voltage becomes unstable due to noise or the like, the vertical size changes.

【0004】その変動を抑えるため抵抗3及びコンデン
サ4で構成した積分回路11により安定化させる。
In order to suppress the fluctuation, it is stabilized by an integrating circuit 11 composed of a resistor 3 and a capacitor 4.

【0005】そのコンデンサ4の容量が小さいとき、つ
まり積分回路11の時定数が小さいとき(この時の時定
数をT1とする)、周波数・電圧変換回路1の出力2に
図8の(A)ようなノイズが重畳した場合、トランジス
タ6のエミッタ出力波形7が図8の(B)のように変動
する。そこでこのコンデンサ4の容量を大きく、つまり
積分回路11の時定数を大きくすると(この時の時定数
をT2とする)、図8の(C)のように安定する。時定
数T1、T2は T1<T2 である。
When the capacity of the capacitor 4 is small, that is, when the time constant of the integrating circuit 11 is small (the time constant at this time is T1), the output 2 of the frequency / voltage converting circuit 1 is shown in FIG. When such noise is superimposed, the emitter output waveform 7 of the transistor 6 fluctuates as shown in FIG. Therefore, if the capacitance of the capacitor 4 is increased, that is, the time constant of the integrating circuit 11 is increased (the time constant at this time is T2), the capacitor becomes stable as shown in FIG. 8C. The time constants T1 and T2 are T1 <T2.

【0006】しかし積分回路11の時定数がT2のとき
入力信号切換時に周波数・電圧変換回路1の出力2が図
9の(A)のように変化したときトランジスタ6のエミ
ッタ出力波形7が、図9の(C)のように安定するまで
の時間がかかる。この積分回路11の時定数がT1であ
ると図9の(B)のように安定するまでの時間が短くな
る。
However, when the time constant of the integrating circuit 11 is T2 and the output 2 of the frequency / voltage converting circuit 1 changes as shown in FIG. 9A when the input signal is switched, the emitter output waveform 7 of the transistor 6 is As shown in (C) of 9, it takes time to stabilize. If the time constant of the integrating circuit 11 is T1, the time until it becomes stable becomes short as shown in FIG. 9B.

【0007】もしくは、特開平1−114165号公報
のように周波数・電圧変換回路内の積分回路で代用して
いた。
Alternatively, as in Japanese Patent Laid-Open No. 1-114165, an integrating circuit in the frequency / voltage converting circuit is used instead.

【0008】[0008]

【発明が解決しようとする課題】上記従来技術では、信
号切り換え時の垂直サイズの画面応答の速度を優先させ
るか、ノイズ等による垂直サイズ変動防止を優先させる
かの二者択一をするしかなかった。
In the above-mentioned prior art, there is no choice but to give priority to the speed of vertical screen response at the time of signal switching or to prevent vertical size fluctuation due to noise or the like. It was

【0009】本発明の目的は、ノイズ等による垂直サイ
ズ変動をなくし、且つ信号切り換え時における垂直サイ
ズ安定までの時間を短縮することを目的とする。
An object of the present invention is to eliminate vertical size variation due to noise and the like, and to shorten the time until the vertical size stabilizes at the time of signal switching.

【0010】[0010]

【課題を解決するための手段】上記目的は周波数・電圧
変換回路の出力電圧を安定化させるための時定数の大き
な積分回路と垂直サイズの画面応答速度を優先させるた
めの時定数の小さい積分回路を設け、その積分回路を切
り換えるスイッチング手段と入力信号切り換え時にこの
スイッチング手段の出力を切り換える制御回路を設ける
ことにより達成される。
The above object is to provide an integrating circuit having a large time constant for stabilizing the output voltage of the frequency / voltage conversion circuit and an integrating circuit having a small time constant for giving priority to the vertical size screen response speed. And a switching circuit for switching the integration circuit and a control circuit for switching the output of the switching device when switching the input signal.

【0011】また、上記目的は信号切り換え時、積分回
路の出力により自動的にスイッチング手段を切り換える
回路を設けることにより達成される
The above object is also achieved by providing a circuit for automatically switching the switching means by the output of the integrating circuit when the signal is switched.

【0012】[0012]

【作用】本発明の垂直振幅安定化回路の制御回路は図1
に示すように垂直同期信号切り換え時、周波数・電圧変
換回路の出力電圧の変化に応じて積分回路302の出力
電圧が安定するまでの時間だけ積分回路303の出力電
圧をバッファ回路に接続するようにスイッチング手段を
切り換える。その後、積分回路302の出力電圧が安定
した時点で積分回路302の出力電圧をバッファ回路に
接続するようにスイッチング手段を切り換える。ここ
で、積分回路302の時定数は入力電圧変動に対して出
力電圧を安定出来るように設定する。積分回路303の
時定数は積分回路302に比べて充分小さくする。
The control circuit of the vertical amplitude stabilizing circuit of the present invention is shown in FIG.
As shown in, when switching the vertical synchronizing signal, the output voltage of the integrating circuit 303 is connected to the buffer circuit only for the time until the output voltage of the integrating circuit 302 stabilizes according to the change of the output voltage of the frequency / voltage converting circuit. Switching the switching means. After that, when the output voltage of the integrating circuit 302 becomes stable, the switching means is switched so that the output voltage of the integrating circuit 302 is connected to the buffer circuit. Here, the time constant of the integrating circuit 302 is set so that the output voltage can be stabilized against variations in the input voltage. The time constant of the integrating circuit 303 is made sufficiently smaller than that of the integrating circuit 302.

【0013】これにより信号切り換え時の垂直サイズ変
動を低減し、且つ定常状態には外来ノイズ等に対して垂
直サイズ変動を防止することができる。
As a result, it is possible to reduce the vertical size variation at the time of signal switching, and to prevent the vertical size variation from being caused by external noise in the steady state.

【0014】また、上記の制御回路と同じ働きをスイッ
チング手段自体にもたせた方法も図2に記載する。垂直
同期信号切り換え時、周波数・電圧変換回路の出力電圧
の変化に応じて、積分回路302の出力電圧が安定する
までの時間は積分回路303が早く安定することにより
スイッチング手段を切り換えて積分回路303の出力電
圧をバッファ回路に接続する。その後、積分回路302
の出力電圧が充分安定した時点で積分回路302の出力
電圧をバッファ回路に接続するようにスイッチング手段
を切り換えることにより目的を達成できる。
FIG. 2 also shows a method in which the switching means itself has the same function as the above control circuit. When the vertical synchronizing signal is switched, the integration circuit 303 stabilizes quickly until the output voltage of the integration circuit 302 stabilizes in accordance with the change in the output voltage of the frequency / voltage conversion circuit. The output voltage of is connected to the buffer circuit. Then, the integrating circuit 302
The object can be achieved by switching the switching means so that the output voltage of the integrating circuit 302 is connected to the buffer circuit when the output voltage of 1 is sufficiently stabilized.

【0015】[0015]

【実施例】図6は本発明の一実施例を示す。FIG. 6 shows an embodiment of the present invention.

【0016】周波数・電圧変換回路1は入力垂直同期信
号の周波数に応じた電圧を出力する。
The frequency / voltage conversion circuit 1 outputs a voltage corresponding to the frequency of the input vertical synchronizing signal.

【0017】その出力を抵抗3とコンデンサ4で構成さ
れた積分回路11によりノイズ等による電圧変動をなく
し安定化させる。積分回路11の時定数は、積分回路1
6の時定数より大きくする。この積分回路11により安
定化された電圧はトランジスタ6を介し垂直振幅制御回
路10に入力される。
The output is stabilized by eliminating the voltage fluctuation due to noise etc. by an integrating circuit 11 composed of a resistor 3 and a capacitor 4. The time constant of the integrating circuit 11 is equal to the integrating circuit 1
It should be larger than the time constant of 6. The voltage stabilized by the integrating circuit 11 is input to the vertical amplitude control circuit 10 via the transistor 6.

【0018】低い周波数から高い周波数へ入力信号が切
り替わるとき、周波数・電圧変換回路1の出力電圧が図
10の(A)のように変化すると積分回路11の出力
は、時定数が大きいため図10の(B)のように瞬時に
出力電圧が一定にならない。この間、時定数の小さい積
分回路16が図10(C)のように立上り、図10
(D)に示す期間トランジスタ12がONし図10
(E)のように積分回路16によりいち早く安定化され
た電圧を垂直振幅制御回路に入力される。
When the input signal is switched from the low frequency to the high frequency and the output voltage of the frequency / voltage conversion circuit 1 changes as shown in FIG. 10A, the output of the integration circuit 11 has a large time constant, and therefore the output of FIG. The output voltage does not become constant instantaneously as in (B). During this period, the integrating circuit 16 having a small time constant rises as shown in FIG.
The transistor 12 is turned on for the period shown in FIG.
The voltage stabilized by the integrating circuit 16 as shown in (E) is input to the vertical amplitude control circuit.

【0019】逆に信号が高い周波数から低い周波数切り
換わるとき周波数・電圧変換回路1の出力電圧は下がる
ので、ダイオ−ド17が同通してコンデンサ4に溜った
電荷を時定数の小さい積分回路16より放電させ積分回
路11の出力が一定になる時間を短縮し、いち早く安定
化された電圧を垂直振幅制御回路に入力される。
On the contrary, when the signal is switched from the high frequency to the low frequency, the output voltage of the frequency / voltage conversion circuit 1 is lowered, so that the charge accumulated in the capacitor 4 through the diode 17 is integrated into the integration circuit 16 having a small time constant. The time during which the output of the integrator circuit 11 becomes constant by further discharging is shortened, and the stabilized voltage is input to the vertical amplitude control circuit as soon as possible.

【0020】本発明によれば、安価な回路でノイズ等に
よる垂直サイズ変動をなくし、且つ信号切り換え時にお
ける垂直振幅が安定するまでの時間を短縮する効果があ
る。
According to the present invention, there is an effect that an inexpensive circuit eliminates vertical size variation due to noise and the like, and shortens the time until the vertical amplitude stabilizes at the time of signal switching.

【0021】[0021]

【発明の効果】以上のように本発明によれば、周波数・
電圧変換回路の出力を安定にし、信号切り換え時におけ
る垂直振幅の安定する時間を短縮することができる。
As described above, according to the present invention, the frequency
It is possible to stabilize the output of the voltage conversion circuit and shorten the time for the vertical amplitude to stabilize during signal switching.

【図面の簡単な説明】[Brief description of drawings]

【図1】垂直振幅安定化回路1を示す図である。FIG. 1 is a diagram showing a vertical amplitude stabilization circuit 1.

【図2】垂直振幅安定化回路2を示す図である。FIG. 2 is a diagram showing a vertical amplitude stabilizing circuit 2;

【図3】マルチスキャンディスプレイのブロック図であ
る。
FIG. 3 is a block diagram of a multi-scan display.

【図4】垂直励振回路周辺のブロック図である。FIG. 4 is a block diagram around a vertical excitation circuit.

【図5】垂直振幅安定化回路の従来技術を示す図であ
る。
FIG. 5 is a diagram showing a conventional technique of a vertical amplitude stabilizing circuit.

【図6】本発明の垂直振幅安定化回路の一実施例を示す
図である。
FIG. 6 is a diagram showing an embodiment of a vertical amplitude stabilizing circuit of the present invention.

【図7】周波数・電圧変換回路1の入出力の特性図であ
る。
FIG. 7 is a characteristic diagram of input / output of the frequency / voltage conversion circuit 1.

【図8】周波数・電圧変換回路の出力にノイズが重畳し
たときの各波形図である。
FIG. 8 is a waveform diagram when noise is superimposed on the output of the frequency / voltage conversion circuit.

【図9】信号切り換え時の各波形図である。FIG. 9 is a waveform diagram when signals are switched.

【図10】垂直振幅安定化回路における各部波形図であ
る。
FIG. 10 is a waveform chart of each part in the vertical amplitude stabilization circuit.

【符号の説明】[Explanation of symbols]

1…周波数・電圧変換回路、 3…抵抗、 4…コンデンサ、 6…トランジスタ、 8…抵抗、 9…抵抗、 10…垂直振幅制御回路、 11…積分回路、 12…トランジスタ、 13…抵抗、 14…抵抗、 15…コンデンサ、 16…積分回路、 17…ダイオード、 103…外部信号入力回路、 102…信号切換回路、 103…ビデオ回路・ビデオ出力回路、 104…マルチ周波数対応同期信号制御回路、 105…ブラウン管ドライブ回路、 106…高圧整流出力回路・フォーカス回路、 107…垂直励振・垂直出力回路、 108…水平励振・水平出力回路、 201…垂直サイズ調節回路、 202…外部入力インターフェース回路、 203…周波数・電圧変換回路、 204…垂直振幅安定化回路、 205…マルチ周波数対応同期信号制御回路、 206…垂直励振回路、 207…垂直振幅制御回路、 208…垂直出力、 209…直線性制御回路、 210…垂直位置制御回路、 301…周波数・電圧変換回路、 302…積分回路、 303…積分回路、 304…スイッチング手段、 305…バッファ回路、 306…垂直振幅安定化回路、 307…垂直振幅制御回路。 1 ... Frequency / voltage conversion circuit, 3 ... Resistor, 4 ... Capacitor, 6 ... Transistor, 8 ... Resistor, 9 ... Resistor, 10 ... Vertical amplitude control circuit, 11 ... Integrating circuit, 12 ... Transistor, 13 ... Resistor, 14 ... Resistor, 15 ... Capacitor, 16 ... Integrator circuit, 17 ... Diode, 103 ... External signal input circuit, 102 ... Signal switching circuit, 103 ... Video circuit / video output circuit, 104 ... Multi-frequency compatible sync signal control circuit, 105 ... CRT Drive circuit, 106 ... High-voltage rectification output circuit / focus circuit, 107 ... Vertical excitation / vertical output circuit, 108 ... Horizontal excitation / horizontal output circuit, 201 ... Vertical size adjustment circuit, 202 ... External input interface circuit, 203 ... Frequency / voltage Conversion circuit, 204 ... Vertical amplitude stabilization circuit, 205 ... Multi-frequency compatible synchronization signal system Circuits, 206 ... Vertical excitation circuit, 207 ... Vertical amplitude control circuit, 208 ... Vertical output, 209 ... Linearity control circuit, 210 ... Vertical position control circuit, 301 ... Frequency / voltage conversion circuit, 302 ... Integrating circuit, 303 ... Integral Circuit, 304 ... Switching means, 305 ... Buffer circuit, 306 ... Vertical amplitude stabilizing circuit, 307 ... Vertical amplitude control circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】周波数の異なる垂直同期信号に応じた電圧
を発生する周波数・電圧変換回路とその出力電圧の変動
を安定化させる時定数の異なる複数の積分回路とその出
力を垂直振幅制御回路へ接続するバッファ回路と、この
積分回路を切り換えるスイッチング手段とその動作時間
を制御する制御回路を備えたことを特徴とする垂直振幅
安定化回路を有する画像表示装置。
1. A frequency / voltage conversion circuit for generating a voltage corresponding to a vertical synchronizing signal having a different frequency, a plurality of integration circuits having different time constants for stabilizing fluctuations of its output voltage, and its output to a vertical amplitude control circuit. An image display device having a vertical amplitude stabilizing circuit, comprising a buffer circuit to be connected, switching means for switching the integrating circuit, and a control circuit for controlling the operation time thereof.
【請求項2】請求項1記載の垂直振幅安定化回路におい
て、積分回路の出力電圧により自動的にスイッチング手
段を切り換えることを特徴とした垂直振幅安定化回路を
有する画像表示装置。
2. An image display device having a vertical amplitude stabilizing circuit according to claim 1, wherein the switching means is automatically switched by the output voltage of the integrating circuit.
JP910394A 1994-01-31 1994-01-31 Image display device having vertical amplitude stabilizing circuit Pending JPH07222024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP910394A JPH07222024A (en) 1994-01-31 1994-01-31 Image display device having vertical amplitude stabilizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP910394A JPH07222024A (en) 1994-01-31 1994-01-31 Image display device having vertical amplitude stabilizing circuit

Publications (1)

Publication Number Publication Date
JPH07222024A true JPH07222024A (en) 1995-08-18

Family

ID=11711298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP910394A Pending JPH07222024A (en) 1994-01-31 1994-01-31 Image display device having vertical amplitude stabilizing circuit

Country Status (1)

Country Link
JP (1) JPH07222024A (en)

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