JPH05274787A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH05274787A
JPH05274787A JP4017401A JP1740192A JPH05274787A JP H05274787 A JPH05274787 A JP H05274787A JP 4017401 A JP4017401 A JP 4017401A JP 1740192 A JP1740192 A JP 1740192A JP H05274787 A JPH05274787 A JP H05274787A
Authority
JP
Japan
Prior art keywords
current
circuit
output
voltage
mute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4017401A
Other languages
Japanese (ja)
Other versions
JP2797809B2 (en
Inventor
Kunihiko Azuma
邦彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4017401A priority Critical patent/JP2797809B2/en
Publication of JPH05274787A publication Critical patent/JPH05274787A/en
Application granted granted Critical
Publication of JP2797809B2 publication Critical patent/JP2797809B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the output of an excessive signal at the time of conducting a switch in an automatic gain control circuit containing a switch circuit for connecting/disconnecting an output signal directly in a loop. CONSTITUTION:A mute pulse is inputted to a mute switch 7 and a current source 21 in common through a mute pulse input terminal 20. In the state of that the mute switch 7 is turned off by the mute pulse, a current whose absolute value is larger and whose polarity is opposite to the current outputted from a comparator 16 is outputted by the current source 21. Thus, a voltage generated in a hold capacitor C2 is set so that the gain of a first voltage control amplifier circuit 2 becomes a minimum. In the transitional state of that the mute pulse disappears, since the gain of the first voltage control amplifier circuit is converged to a setting level applied to a first control signal input terminal gradually from the minimum, an excessive recording current is not outputted to a recording current output terminal 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、自動利得制御回路に関
し、特に磁気記録再生装置の記録増幅回路の自動利得制
御回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit, and more particularly to an automatic gain control circuit for a recording / amplifying circuit of a magnetic recording / reproducing apparatus.

【0002】[0002]

【従来の技術】従来の磁気記録再生装置の記録増幅回路
の自動利得制御回路を図3に示す。第1の電圧制御増幅
回路2は、第1の入力端子1を介して与えらえる周波数
変調された輝度信号を増幅し、加算回路3に出力する。
第2の電圧制御増幅回路5は,第2の入力端子4を介し
て与えられる低域変換色信号を、第2の制御信号入力端
子6に与えられる制御電圧に応じた増幅率で増幅し、加
算回路3に出力する。加算回路3は、第1の電圧制御増
幅回路2の出力と、第2の電圧制御増幅回路5の出力を
加算し、ミュートパルス入力端子20に与えられるミュ
ートパルスにより制御されるミュートスイッチ7を介し
て端子8に出力する。端子8は、第1のコンデンサC1
と第1の抵抗R1の直列回路から成る電圧−電流変換回
路9を介して端子10に接続される。ここで、端子10
は、電流増幅回路11の入力に接続されているが、電流
増幅回路11の入力インピーダンスは電圧−電流変換回
路9のインピーダンスに対して10%のオーダーとなる
様低く設定されているので、端子8に出力された電圧
は、その電圧を電圧−電流変換回路9のインピーダンス
で割った値とほぼ等しい電流に変換されて、端子10を
介して電流増幅回路11に与えられる。電流増幅回路1
1は、端子10に流入する電流を増幅し、記録電流出力
端子12を介して記録ヘッドL1に出力する。ダンピン
グ抵抗R2は、電流増幅回路11の出力容量、及び記録
ヘッドL1までの配線が有する浮遊容量等と、記録ヘッ
ドL1のインダクタンスとの共振よって生じる記録電流
の周波数に対する変動を緩和するために、記録電流出力
端子12と接地間に接続される。記録ヘッドL1を流れ
る電流は記録電流検出端子13を介して記録電流検出回
路14を与えられて電圧に変換され、検波回路15によ
り検波されて比較回路16に与えられる。
2. Description of the Related Art FIG. 3 shows an automatic gain control circuit of a recording amplifier circuit of a conventional magnetic recording / reproducing apparatus. The first voltage control amplifier circuit 2 amplifies the frequency-modulated luminance signal provided via the first input terminal 1 and outputs it to the adder circuit 3.
The second voltage control amplifier circuit 5 amplifies the low-frequency conversion color signal given through the second input terminal 4 with an amplification factor according to the control voltage given to the second control signal input terminal 6, Output to the adder circuit 3. The adder circuit 3 adds the output of the first voltage-controlled amplifier circuit 2 and the output of the second voltage-controlled amplifier circuit 5, and via the mute switch 7 controlled by the mute pulse applied to the mute pulse input terminal 20. Output to terminal 8. Terminal 8 is the first capacitor C1
And a first resistor R1 are connected to a terminal 10 via a voltage-current conversion circuit 9 formed of a series circuit. Here, the terminal 10
Is connected to the input of the current amplifying circuit 11, but the input impedance of the current amplifying circuit 11 is set so low as to be on the order of 10% of the impedance of the voltage-current converting circuit 9, so that the terminal 8 The voltage output to is converted into a current substantially equal to a value obtained by dividing the voltage by the impedance of the voltage-current conversion circuit 9, and is supplied to the current amplification circuit 11 via the terminal 10. Current amplifier circuit 1
1 amplifies the current flowing into the terminal 10 and outputs it to the recording head L1 via the recording current output terminal 12. The damping resistor R2 reduces the variation in the recording current with respect to the frequency due to the resonance of the output capacitance of the current amplification circuit 11, the stray capacitance of the wiring to the recording head L1, and the inductance of the recording head L1. It is connected between the current output terminal 12 and the ground. The current flowing through the recording head L1 is supplied to the recording current detection circuit 14 via the recording current detection terminal 13, converted into a voltage, detected by the detection circuit 15 and supplied to the comparison circuit 16.

【0003】比較回路16は、第1の制御信号入力端子
17を介して与えられる制御電圧と、検波回路15の出
力電圧との比較を、水平同期信号入力端子18を介して
与えられる水平同期信号が存在する期間においてのみ行
なう。比較によって生じた差は、電流として制御電圧出
力端子19を介してホールドコンデンサC2に出力され
る。比較回路16の出力電流がホールドコンデンサに充
放電されて発生した電圧は、第1の電圧制御増幅回路2
の利得制御電圧として帰還される。
The comparison circuit 16 compares the control voltage applied via the first control signal input terminal 17 with the output voltage of the detection circuit 15 and outputs the horizontal sync signal applied via the horizontal sync signal input terminal 18. Only during the period that there is. The difference generated by the comparison is output as a current to the hold capacitor C2 via the control voltage output terminal 19. The voltage generated by charging and discharging the output current of the comparison circuit 16 in the hold capacitor is the first voltage control amplifier circuit 2
It is fed back as the gain control voltage.

【0004】次に、動作について説明を行なう。記録ヘ
ッドL1には、第1の入力端子1に与えられる周波数変
調された輝度信号と、第2の入力端子4に与えられる低
域変換色信号それぞれに比例した電流を重ね合わせた電
流が流れる。この記録電流の振幅は記録電流検出回路1
4,検波回路15により検出され、第1の制御信号入力
端子17に与えられる制御信号と比較回路16により比
較される。比較回路16は、水平同期信号入力端子18
に水平同期信号が与えられている期間についてのみ比較
動作を行なうが、水平同期信号が存在する期間では、低
域変換色信号が存在しないため検波回路15は周波数変
調された輝度信号成分だけから成る記録電流の振幅を検
出する。したがって比較回路16は低域変換色信号には
全く干渉されずに、周波数変調された輝度信号のみの振
幅と、第1の制御信号入力端子に与えられた制御信号の
差を検出し、その差をホールドコンデンサC2の充放電
電流として出力する。検出された記録電流振幅が第1の
制御信号入力端子17に与えられた電圧よりも小なら
ば、第1の電圧制御増幅回路2の利得が増大する様に、
逆に、検出された記録電流振幅が第1の制御信号入力端
子17に与えられた電圧よりも大ならば、第1の電圧制
御増幅回路2の利得が減少する様に、比較回路16の出
力電流は設定されている。したがって、常に記録電流振
幅と第1の制御信号入力端子17の制御信号は一致する
様に第1の電圧制御増幅回路2の利得が制御される帰還
回路が形成される。これにより、第1の制御信号入力端
子に与えられる制御電圧に応じた記録電流振幅を有する
周波数変調された輝度信号が記録ヘッドL1に常に流れ
る様、自動利得制御が行なわれる。
Next, the operation will be described. A current obtained by superimposing a frequency-modulated luminance signal applied to the first input terminal 1 and a current proportional to the low-frequency conversion color signal applied to the second input terminal 4 flows through the recording head L1. The amplitude of the recording current is the recording current detection circuit 1
4, detected by the detection circuit 15 and compared with the control signal applied to the first control signal input terminal 17 by the comparison circuit 16. The comparison circuit 16 has a horizontal synchronization signal input terminal 18
The comparison operation is performed only during the period when the horizontal synchronizing signal is applied to the detection circuit 15. However, during the period when the horizontal synchronizing signal is present, the low-pass conversion chrominance signal is not present, so the detection circuit 15 is composed of only the frequency-modulated luminance signal component. The amplitude of the recording current is detected. Therefore, the comparison circuit 16 detects the difference between the amplitude of only the frequency-modulated luminance signal and the control signal applied to the first control signal input terminal without interfering with the low-frequency conversion color signal, and the difference is detected. Is output as a charge / discharge current of the hold capacitor C2. If the detected recording current amplitude is smaller than the voltage applied to the first control signal input terminal 17, the gain of the first voltage control amplifier circuit 2 increases,
On the contrary, if the detected recording current amplitude is larger than the voltage applied to the first control signal input terminal 17, the output of the comparison circuit 16 is set so that the gain of the first voltage control amplifier circuit 2 decreases. The current is set. Therefore, a feedback circuit is formed in which the gain of the first voltage control amplifier circuit 2 is controlled so that the recording current amplitude and the control signal of the first control signal input terminal 17 always match. As a result, automatic gain control is performed so that a frequency-modulated luminance signal having a recording current amplitude corresponding to the control voltage applied to the first control signal input terminal always flows through the recording head L1.

【0005】次に、ミュートスイッチ7の動作について
説明を行なう。ミュートスイッチ7は、図3に示す記録
増幅回路が動作状態の時、記録電流出力端子12に信号
成分が出力されていない状態を得る様、ミュートパルス
入力端子20に与えられるミュートパルスにより制御さ
れる。これは、既に記録済みの信号に対して、一時的に
重ね書きを行いながら、既に記録済の信号との連続性を
保って記録を行なうつなぎ撮りと呼ばれる記録等を行な
う為に、記録電流出力端子12に流れる記録電流の断続
を高速に行なう為のものである。
Next, the operation of the mute switch 7 will be described. The mute switch 7 is controlled by a mute pulse applied to the mute pulse input terminal 20 so as to obtain a state in which no signal component is output to the recording current output terminal 12 when the recording amplifier circuit shown in FIG. 3 is in operation. .. This is because the recording current output is performed in order to perform recording, such as joint recording, in which the recorded signal is temporarily overwritten while maintaining continuity with the already recorded signal. The purpose is to interrupt the recording current flowing through the terminal 12 at high speed.

【0006】[0006]

【発明が解決しようとする課題】この従来の記録増幅回
路の自動利得制御回路では、つなぎ撮り等を行なう為の
ミュートスイッチが自動利得制御回路の帰還ループ内に
入る事となる。これにより、周波数変調された輝度信号
が入力された状態で、ミュートスイッチが切れている場
合には、記録ヘッドには全く記録電流が現れないので、
自動利得制御を行なう電圧制御増幅回路に帰還される制
御電圧は、利得が最大となる様設定される。この状態か
ら、ミュートスイッチが導通状態となる過渡的状態で
は、周波数変調された輝度信号入力を最大の利得で増幅
してしまう為、一時的に記録ヘッドには過大な記録電流
が流れてしまう。この様な過大なヒゲ状の記録電流は、
記録に適した値と異なっており、再生時にはミュートス
イッチの切換ポイントの画面上にスジ状の白い線がでて
しまう。この為、つなぎ撮りによりテープに記録した画
像は、つなぎ撮りを開始した時点での画質が劣化してし
まっており、再生した場合には非常に見苦しいものとな
る欠点が有る。
In the conventional automatic gain control circuit of the recording amplification circuit, the mute switch for performing joint photographing or the like is placed in the feedback loop of the automatic gain control circuit. As a result, when the frequency-modulated luminance signal is input and the mute switch is turned off, no recording current appears in the recording head.
The control voltage fed back to the voltage control amplifier circuit that performs automatic gain control is set so that the gain becomes maximum. From this state, in a transitional state in which the mute switch is in a conductive state, the frequency-modulated luminance signal input is amplified with the maximum gain, so that an excessive recording current temporarily flows in the recording head. Such an excessive mustache-shaped recording current
The value is different from the value suitable for recording, and a streak-shaped white line appears on the screen at the switching point of the mute switch during playback. Therefore, the image recorded on the tape by the joint shooting has a drawback that the image quality at the time of starting the joint shooting is deteriorated and becomes very unsightly when reproduced.

【0007】[0007]

【課題を解決するための手段】本発明の自動利得制御回
路は、入力信号を増幅する電圧制御増幅回路と、第1の
制御信号入力を備え前記電圧制御増幅回路の出力を入力
とするスイッチ手段と、前記スイッチ手段の出力を入力
とする検波回路と、前記検波回路の出力を保持する容量
と、前記容量に発生した電圧を前記電圧制御増幅回路に
帰還する帰還路と、前記容量に出力を接続し、前記第1
の制御信号入力と共通接続した第2の制御信号入力を有
する電流源とを備えている。
SUMMARY OF THE INVENTION An automatic gain control circuit according to the present invention comprises a voltage control amplifier circuit for amplifying an input signal and a switch means for receiving an output of the voltage control amplifier circuit as a first control signal input. A detection circuit that receives the output of the switch means, a capacitor that holds the output of the detection circuit, a feedback path that returns the voltage generated in the capacitor to the voltage control amplifier circuit, and an output to the capacitor. Connect the first
Control signal input and a current source having a second control signal input commonly connected.

【0008】[0008]

【実施例】次に、本発明に図面を参照して説明する。図
1は本発明の第1の実施例のブロック図である。なお、
図3に示す従来例と同一機能を有する所は同一符号をつ
けることとし、かつ説明を省略する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention. In addition,
Parts having the same functions as those of the conventional example shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted.

【0009】電流源21は、ミュートパルス入力端子2
0に与えらえるミュートパルスが与えられるとともに、
その出力が比較回路16の出力と共通に制御電圧出力端
子19を介してホールドコンデンサC2に接続される。
電流源21の出力電流は、ミュートパルスが加わった時
に出力され、その値はミュートパルス入力時に比較回路
16が出力する電流値の絶対値よりも大きく、かつ符号
を逆に設定してある。これによりミュートパルスが入力
された時には比較回路16が第1の電圧制御増幅回路2
の利得を最大にする様出力する電流を打ち消し、ホール
ドコンデンサC2に生ずる電圧は第1の電圧制御増幅回
路の利得を最小にする様に設定される。さらに、ミュー
トパルス入力が無くなった直後では、第1の電圧制御増
幅回路2の利得は最小であるので、記録ヘッドL1には
周波数変調された輝度信号成分が過大に流れる事はな
い。
The current source 21 has a mute pulse input terminal 2
A mute pulse given to 0 is given,
The output is connected to the hold capacitor C2 via the control voltage output terminal 19 in common with the output of the comparison circuit 16.
The output current of the current source 21 is output when a mute pulse is applied, and its value is larger than the absolute value of the current value output by the comparison circuit 16 when the mute pulse is input, and its sign is set to be opposite. Accordingly, when the mute pulse is input, the comparison circuit 16 causes the first voltage control amplifier circuit 2
The output current is canceled to maximize the gain and the voltage generated in the hold capacitor C2 is set to minimize the gain of the first voltage control amplifier circuit. Immediately after the mute pulse input disappears, the gain of the first voltage control amplifier circuit 2 is minimum, so that the frequency-modulated luminance signal component does not flow excessively in the recording head L1.

【0010】さらに、図4を用いて本実施例中の電流源
21を詳細に説明する。NPNトランジスタQ1のベー
スはミュートパルス入力端子20に、コレクタは制御電
圧出力端子19に、エミッタは抵抗R3を介して接地に
それぞれ接続される。ミュートパルス入力端子20に与
えられるミュート時の電圧をE、NPNトランジスタQ
1のベースとエミッタ間電圧をVBEとすれば、NPNト
ランジスタQ1のコレクタにはミュート時においておよ
そ(E−VBE)/R3なる値の電流が出力される。よっ
てR3の値を選択する事により、図1に示した比較回路
16がミュート時に出力する電流を打ち消す様電流源の
出力電流を容易に設定可能である。
Further, the current source 21 in this embodiment will be described in detail with reference to FIG. The base of the NPN transistor Q1 is connected to the mute pulse input terminal 20, the collector is connected to the control voltage output terminal 19, and the emitter is connected to the ground via the resistor R3. The mute voltage applied to the mute pulse input terminal 20 is E, the NPN transistor Q
Assuming that the voltage between the base and the emitter of 1 is V BE , a current of approximately (E−V BE ) / R3 is output to the collector of the NPN transistor Q1 during mute. Therefore, by selecting the value of R3, the output current of the current source can be easily set so as to cancel the current output by the comparison circuit 16 shown in FIG. 1 during mute.

【0011】次に、本発明の第2の実施例について図面
を参照して説明する。図2は、本発明の第2の実施例の
ブロック図である。なお、図1に示す第1の実施例と同
一機能を有する所は同一符号をつけることとし、かつ、
説明を省略する。
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of the second embodiment of the present invention. In addition, parts having the same functions as those of the first embodiment shown in FIG.
The description is omitted.

【0012】ブランキング回路22は、ミュートパルス
入力端子20に入力が接続されたインバーター23と、
インバーター23の出力及び水平同期信号入力端子が入
力に接続され、比較回路16に出力が接続されるAND
回路から成る。ブランキング回路22は、ミュートパル
ス入力時において比較回路16への水平同期信号の入力
を禁止するので、ミュート時には、ホールドコンデンサ
C2に対して電流を供給するのは電流源21だけとな
る。つまり、第2の実施例においては電流源21の出力
電流は、比較回路16の出力電流と独立に、第1の電圧
制御増幅器2の利得を最小に保つことのできる範囲内で
適当な値に設定できる。したがって本実施例において
は、電流源21の出力電流値の設定の自由度を広げる事
が可能であるという利点が有る。
The blanking circuit 22 includes an inverter 23 whose input is connected to the mute pulse input terminal 20,
The output of the inverter 23 and the horizontal sync signal input terminal are connected to the input, and the output is connected to the comparison circuit 16 AND
Composed of circuits. Since the blanking circuit 22 prohibits the horizontal synchronizing signal from being input to the comparison circuit 16 when the mute pulse is input, only the current source 21 supplies current to the hold capacitor C2 during mute. That is, in the second embodiment, the output current of the current source 21 is set to an appropriate value within the range in which the gain of the first voltage control amplifier 2 can be kept to a minimum independently of the output current of the comparison circuit 16. Can be set. Therefore, the present embodiment has an advantage that the degree of freedom in setting the output current value of the current source 21 can be increased.

【0013】[0013]

【発明の効果】以上説明したように本発明は、自動利得
制御回路内に有る利得制御電圧を保持するホールドコン
デンサに対して、ミュートスイッチと連動する電流源に
より電流を供給する構成とする事にしたので、ミュート
スイッチが切れた状態でもホールドコンデンサに保持さ
れる利得制御電圧が利得を増大させる様変化する事を防
止でき、ミュートスイッチが導通状態に変化した過渡現
象として、過大な出力を生ずる事が無いという効果を有
する。特に磁気記録再生装置の記録増幅回路の自動利得
制御増幅回路として使用した場合には、つなぎ撮り等を
行なった場合の画像の劣化を防止できる。
As described above, according to the present invention, the holding capacitor for holding the gain control voltage in the automatic gain control circuit is supplied with the current by the current source working in conjunction with the mute switch. Therefore, even when the mute switch is off, it is possible to prevent the gain control voltage held in the hold capacitor from changing so as to increase the gain. There is an effect that there is no. In particular, when it is used as an automatic gain control amplifier circuit of a recording amplifier circuit of a magnetic recording / reproducing apparatus, it is possible to prevent deterioration of an image when a joint shooting or the like is performed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例のブロック図である。FIG. 1 is a block diagram of a first embodiment of the present invention.

【図2】本発明の第2の実施例のブロック図である。FIG. 2 is a block diagram of a second embodiment of the present invention.

【図3】従来例のブロック図である。FIG. 3 is a block diagram of a conventional example.

【図4】図1に示した電流源21の回路図である。FIG. 4 is a circuit diagram of a current source 21 shown in FIG.

【符号の説明】[Explanation of symbols]

1 第1の入力端子 2 第1の電圧制御増幅回路 3 加算回路 4 第2の入力端子 5 第2の電圧制御増幅回路 6 第2の制御信号入力端子 7 ミュートスイッチ 8 端子 9 電圧−電流変換回路 10 端子 11 電流増幅回路 12 記録電流出力端子 13 記録電流検出端子 14 記録電流検出回路 15 検波回路 16 比較回路 17 第1の制御信号入力端子 18 水平同期信号入力端子 19 制御電圧出力端子 20 ホールドコンデンサ 21 電流源 1 1st input terminal 2 1st voltage control amplification circuit 3 addition circuit 4 2nd input terminal 5 2nd voltage control amplification circuit 6 2nd control signal input terminal 7 mute switch 8 terminal 9 voltage-current conversion circuit 10 terminals 11 current amplification circuit 12 recording current output terminal 13 recording current detection terminal 14 recording current detection circuit 15 detection circuit 16 comparison circuit 17 first control signal input terminal 18 horizontal synchronization signal input terminal 19 control voltage output terminal 20 hold capacitor 21 Current source

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電圧制御増幅回路と、第1の制御信号入
力を有し、前記電圧制御増幅回路の出力を入力とするス
イッチ手段と、前記スイッチ手段の出力を入力とする検
波回路と、前記検波回路出力に接続され、前記検波回路
出力を保持する容量と、前記容量に発生する電圧を前記
電圧制御増幅回路に帰還する帰還路とを有する自動利得
制御回路において、前記容量に出力が接続され、前記第
1の制御信号入力と共通接続した第2の制御信号入力を
有する電流源を備える事を特徴とする自動利得制御回
路。
1. A voltage-controlled amplifier circuit, a switch means having a first control signal input and having an output of the voltage-controlled amplifier circuit as an input, a detection circuit having an output of the switch means as an input, In an automatic gain control circuit, which is connected to the output of the detection circuit and holds the output of the detection circuit, and a feedback path for returning the voltage generated in the capacity to the voltage control amplifier circuit, the output is connected to the capacity. An automatic gain control circuit comprising a current source having a second control signal input commonly connected to the first control signal input.
JP4017401A 1992-02-03 1992-02-03 Automatic gain control circuit Expired - Fee Related JP2797809B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4017401A JP2797809B2 (en) 1992-02-03 1992-02-03 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4017401A JP2797809B2 (en) 1992-02-03 1992-02-03 Automatic gain control circuit

Publications (2)

Publication Number Publication Date
JPH05274787A true JPH05274787A (en) 1993-10-22
JP2797809B2 JP2797809B2 (en) 1998-09-17

Family

ID=11942975

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4017401A Expired - Fee Related JP2797809B2 (en) 1992-02-03 1992-02-03 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JP2797809B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878981A (en) * 1994-09-07 1996-03-22 Nec Corp Automatic gain control circuit
JPH0877701A (en) * 1994-09-07 1996-03-22 Nec Corp Recording device
US6809572B2 (en) 2002-09-18 2004-10-26 Cirrus Logic, Incorporated Integrated circuit with automatic polarity detection and configuration

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158675U (en) * 1986-03-28 1987-10-08

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158675U (en) * 1986-03-28 1987-10-08

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878981A (en) * 1994-09-07 1996-03-22 Nec Corp Automatic gain control circuit
JPH0877701A (en) * 1994-09-07 1996-03-22 Nec Corp Recording device
US6809572B2 (en) 2002-09-18 2004-10-26 Cirrus Logic, Incorporated Integrated circuit with automatic polarity detection and configuration

Also Published As

Publication number Publication date
JP2797809B2 (en) 1998-09-17

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