JP2942055B2 - Clamp circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit for clamping a video signal, and more particularly to a clamp circuit suitable for use in video equipment such as an electronic still camera.

[0002]

2. Description of the Related Art In recent years, video equipment such as a digital electronic still camera which converts an image into an electric signal by an image pickup device such as a solid-state image pickup device and stores the electric signal in a memory card has been developed.

A video signal handled by such a circuit of a video device is bright when a level of the video signal is higher than a certain reference level, and is dark when a level of the video signal is lower than a certain reference level. Will be displayed. Therefore, if the DC component is lost or the DC component itself fluctuates when the video signal is amplified using an AC-coupled amplifier, the video signal can be subjected to various corrections, Processing such as signal processing cannot be performed accurately. Therefore, a clamp circuit for adding (reproducing) a DC component of a signal to a video signal is used in a circuit of a video device.

[0006] Video equipment such as an electronic still camera also has a clamp circuit. At the first stroke of the shutter release button of the camera, power is started to be supplied to each circuit in the camera including the clamp circuit. The clamp circuit receives a clamp pulse from a signal generation circuit that generates various reference signals and charges the clamp capacitor for each clamp period. When the charging voltage reaches a predetermined level, the clamp circuit enters a steady state, and shooting is performed by the second stroke of the shutter release button.

[0005]

However, in the clamp circuit mounted on the electronic still camera as described above, the power is turned on by the power switch (first stroke) also serving as the release button, and the clamp capacitor is supplied to the clamp capacitor. Since charging is started, it is not possible to perform appropriate photographing until the clamp circuit reaches a steady state. For example, if the second stroke is turned on without a sufficient period after the first stroke, a normal image cannot be obtained because shooting is performed in an insufficient clamping state.
Therefore, in order to supply a large current during the clamp period to charge the clamp capacitor at a high speed and quickly start up the clamp circuit so that a normal image can be taken even in such a case, a large charge current is charged. A circuit was provided. Such a fast clamping circuit, for example,
Even during the imaging operation, the voltage of the power supply such as a battery fluctuates because a large current flows during the clamp-on in synchronization with the clamp pulse. In addition, power supply noise due to voltage fluctuations generated for each clamp pulse is mixed into the video signal, thereby deteriorating the quality of the video. As described above, the fluctuation of the power supply voltage is particularly serious in a device having a small power supply capacity such as a camera.

The present invention solves the above-mentioned problems of the prior art, and enters a steady state immediately after power-on, does not require a large current during an imaging operation, and minimizes the influence on other circuits such as a power supply. It is an object of the present invention to provide a clamp circuit which has been provided.

[0007]

According to the present invention, there is provided a clamp circuit for clamping a reference level of an input signal to a predetermined voltage, the circuit comprising a DC voltage applied to a control input and a DC voltage applied to a control input. Differential amplifying means for amplifying according to the difference between the input signal voltage, voltage supply means for supplying a reference voltage which is a target of the voltage output from the differential amplifying means, and charging the control input of the differential amplifying means A storage means for applying a voltage; a charging means for charging the storage means in accordance with a difference between the voltage amplified by the differential amplifying means and the reference voltage; a feedback means having a variable charging capability; and charging of the feedback means after power-on. Increase your ability,
Thereafter, there is provided variable means for reducing the size.

In this case, the variable means includes means for monitoring the voltage output from the differential amplifying means, and charging of the feedback means until the voltage output from the differential amplifying means reaches a predetermined value after the power is turned on. Means for increasing the capacity and weakening the charging capacity of the feedback means after the output voltage reaches a predetermined value.

In this case, it is preferable that the variable means include means for increasing the charging capacity of the feedback means for a predetermined period after the power is turned on, and reducing the charging capacity of the feedback means after the predetermined period.

In a clamp circuit for clamping a reference level of an input signal to a predetermined voltage, the circuit includes a power storage means for applying a DC voltage to the input signal, and a power storage means for charging the power storage means, which has a variable charging capability. It is characterized by comprising a voltage supply means and switching means for increasing the charging capability of the voltage supply means for a predetermined period after turning on the power, and reducing the charging capability of the voltage supply means after the predetermined period has elapsed. .

[0011]

According to the clamp circuit of the present invention, after the power is turned on,
The power storage means in the circuit is charged with a large charging current, and thereafter the power storage means is charged with a small charging current required for the clamping operation. Thus, the circuit can be brought into a steady state in a short time after the power is turned on, and thereafter, a stable clamping operation can be performed.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a clamp circuit according to the present invention; FIG. 1 shows the configuration of an embodiment of an electronic still camera to which a clamp circuit according to the present invention is applied. In this figure, a signal input circuit 10, a clamp circuit 12, a video processing circuit 14, and a signal generation circuit 16 of the electronic still camera are shown, and parts not directly related to the present invention are shown and described. Is omitted.

The signal input circuit 10 includes a CCD image sensor (not shown), and has a function of converting a video image formed on an image pickup surface of the CCD image sensor into an electric signal. This circuit receives a reference clock from the signal generation circuit 16, generates a transfer clock, and supplies the transfer clock to the CCD image sensor to drive it.
A function of reading a signal from the CD image sensor, amplifying the signal, and outputting the amplified signal to the clamp circuit 12.

The clamp circuit 12 is a circuit for clamping the video signal 100 transferred from the signal input circuit 10. In the following description, the reference numerals of the signals are indicated by the reference numerals of the connecting lines that appear. The clamp circuit 12 clamps the voltage of the video signal 100 during the clamping period to the reference level (VR), maintains this voltage until the next clamping period, and outputs it to the video processing circuit 14. More specifically, the clamp circuit 12 includes an amplifier (AMP) 18. The amplifier 18 has an output 100 of the signal input circuit 10 connected to its non-inverting input (+), and amplifies the video signal of the input 100. An amplifier that outputs to its output 102. The output 102 of the amplifier 18 forms, on the one hand, the output of the clamping circuit 12 and, on the other hand, the non-inverting input of the comparator 20.
(+), And further connected to the non-inverting input (+) of the differential amplifier (FBC) 24.

The comparator 20 has an inverting input (-) 104 to which a comparison voltage source 22 for generating a comparison voltage Vcomp is connected. The comparator 20 monitors the voltage of the input 102 and determines the magnitude of this voltage and the voltage of the input 104. A voltage determining circuit for generating the determined output as a switching signal at the output 106 is provided. This output 10
6 is connected to the differential amplifier 24. Differential amplifier 24
Has an output 102 of the amplifier 18 connected to its non-inverting input (+). The differential amplifier 24 has an inverting input (-) 108 to which a reference voltage source 26 for generating a reference voltage VR is connected.
The output corresponding to the difference between the voltages of 102 and 108 is output 110.
Is formed. This output 110
Is grounded via a clamp capacitor (C) 28 on the one hand and connected to the inverting input (-) of the amplifier 18 on the other hand. This allows differential amplifier 24
Form a feedback path for the amplifier 18. Further, the differential amplifier 24 receives a clamp pulse (C
In response to (P), when the clamp pulse is at a high level, that is, during the clamp period, a charging current for charging the capacitor 28 is generated at the output 110, and is stopped during the period other than the clamp period to disconnect the connection with the capacitor 28. And has a function of preventing the capacitor 28 from discharging. When the voltage VC stored by the differential amplifier 24 decreases, the voltage of the inverting input 110 to the amplifier 18 decreases.
Increase the voltage VA at the output 102 at 18. Conversely, when the stored voltage VC increases, the voltage of the inverting input 110 to the amplifier 18 increases, and the input potential difference of the amplifier 18 becomes relatively small, so that the voltage VA of the output 102 of the amplifier 18 decreases.

Next, the internal configuration of the differential amplifier 24 described here will be described below. Referring to FIG.
Is shown. The circuit comprises transistors Q1 and Q2, which have non-inverting inputs (+) 120 and inverting inputs (-) 122 at their bases.
A differential amplifier circuit is provided for receiving and amplifying a signal, and the emitters 124 and 126 are both connected to the collector 128 of the transistor Q3. Transistor Q3 is an emitter
130 through a resistor RC, the transistor Q4 has an emitter 13
2 is grounded via a resistor RC, and the collector 134 and base of the transistor Q4 are connected.

The current I1 is applied to the collector 134.
Is connected to the current source 30 for supplying
The contact S2a of the switch S2 controlled by the signal output from the switch S2 is connected. The additional current source 32 for supplying the current I2 is connected to S2b of the switch S2. When the signal 106 is output from the output 106 of the comparator 20, the switch S2b is switched to the contact S2a. Therefore, the switch S2 has a current variable function in which the additional current source 32 and the current source 30 are connected in parallel to supply the current I1 and the current I2 to the collector 134. When the signal Hi is output from the output 106 of the comparator 20, the switch S2 is switched to the contact S2c. The transistors Q3 and Q4 constitute a current mirror circuit in which the same amount of current IB as the current supplied from these current sources to the collector 134 is reflected on the collector 128 of the transistor Q3. The current source 30 and the additional current source 32 generate a current in response to the clamp pulse supplied from the signal generating circuit 16, and supply the generated current to the collector 134 of the transistor Q4.

On the other hand, the collector and base of the transistor Q5 are connected to the collector 136 of the transistor Q1,
It is also connected to the base of the transistor Q6 to form a current mirror circuit in which the same amount of current as the current IB1 flowing through the collector 136 of the transistor Q1 flows between the emitter and collector of the transistor Q6. Similarly, the collector and the base of the transistor Q7 are connected to the collector 138 of the transistor Q2, and also connected to the base of the transistor Q8, so that the same amount of current as the current IB2 flowing through the collector 138 of the transistor Q2 Emitter
A current mirror circuit is formed between the collectors and flows. Further, the collectors 14 of the transistors Q6 and Q8
0 and 142 are connected to the collectors of transistors Q9 and Q10, respectively, and transistors Q9 and Q10 also form a current mirror circuit. Because of this transistor
The same amount of current as the emitter-collector current IB2 of Q7 flows between the emitter and collector of transistor Q10. At this time, a current IC of the same amount as this current flows in the transistor Q9 in a mirror-like manner between the emitter and the collector, so that the current IB1 and the current IB are output from the output line 110 connected to the collector of the transistor Q9.
2 is divided and output as a current IX.
Causes the clamp capacitor 28 to charge. This charging current IX
Is a transistor by the current source 30 and the additional current source 32.
It changes according to the current supplied to Q4.

Returning to FIG. 1, the video processing circuit 14 generates a luminance signal, a chrominance signal, and the like from the DC signal reproduced and output by the clamp circuit 12 based on the video signal, and performs gamma correction and the like. And a circuit for performing video signal processing such as analog / digital conversion.

The signal generating circuit 16 has a function of supplying various reference signals to each section of the electronic still camera in synchronization with a self-running reference clock. In particular, the signal generation circuit 16
The output 112 has a function of generating a clamp pulse (CP). As shown in FIG. 3D, the signal generation circuit 16 is a circuit section that generates a clamp pulse synchronized with a blanking period of a video signal after power is turned on. The generated clamp pulse is output to the clamp circuit 12 of FIG. 1 to turn on / off the feedback operation of the differential amplifier 20. Thus, the comparator 20, the comparison voltage source 22, the current source
30, additional current source 32, switch S1, and signal generation circuit 16
Constitutes a signal generation circuit that generates a signal for controlling the differential amplifier 24. The signal generation circuit 16 includes a switch S1 corresponding to the first stroke of the shutter button. When the first stroke of the shutter button is pressed, the switch S1 is turned on in conjunction with this. In the first stroke of the shutter button, a power supply circuit (not shown) is turned on, and power is supplied from the power supply circuit to each unit of the electronic still camera.

The operation of the clamp circuit according to the present embodiment having the above configuration will be described below with reference to FIGS. 3, (A) shows the ON / OFF state of the switch S1, (B) shows the output state of the comparator 20, (C) shows the switching state of the current source of the differential amplifier 24, (D) shows the output timing of the clamp pulse, (E) shows the voltage VA at the output node A of the amplifier 18, respectively. First, the switch S1 is turned on in conjunction with the first stroke of the shutter button
(T0 in FIG. 3A) and the switch S1 is turned on, power is supplied to each circuit unit. Signal generation circuit when power is turned on
16 outputs a clamp pulse (FIG. 3 (D)). The differential amplifier 24 receives the clamp pulse and responds to the pulse signal.

When the power is turned on, the voltage VC of the inverting input 110 of the amplifier 18 is zero, and the output voltage VA of the amplifier 18 is increased by the voltage of the video signal input to the non-inverting input 100. On the other hand, a voltage VA is applied to the non-inverting input 102 of the comparator 20, and a comparison voltage source is applied to the inverting input 104.
The voltage Vcomp is applied from 22. Immediately after the power is turned on, the voltage VA is lower than the voltage Vcomp.
The comparator 20 outputs a low-level signal from its output 106.
Low is output to the differential amplifier 24. Next, as shown in FIG. 2, the signal Low is input to the differential amplifier 24 and the switch S2 is turned on.
When S2b is connected to contact S2a, current I2 is added to current I1 and these are supplied to collector 134 of transistor Q4. At this time, the same current IB as the amount obtained by adding the current I2 to the current I1 is supplied to the collector 128 of the transistor Q3.

On the other hand, currents IB1 and IB2 are supplied to the collectors of transistors Q5 and Q7, respectively, by voltage VR applied to inverting input 122 and voltage VA applied to non-inverting input 120. Along with this, transistors Q6 and
The current IB1 and the current IB2 are supplied to Q8, respectively. At this time, since the clamp capacitor 28 connected to the output 110 of the differential amplifier 24 is in a discharged state, the transistor
The current IB1 flows from Q6 as the current IX and is charged,
VC rises.

Returning to FIG. 1, when the voltage VC rises, the amplifier
Since the voltage at the 18 inverting input 110 rises, the non-inverting input 100
As a result, the input potential difference between the output 102 and the amplifier 18 decreases, and the amplifier 18 operates to decrease the voltage VA of the output 102. On the other hand, the differential amplifier 24
As the voltage VA decreases, the input potential difference from the voltage VR decreases, and the capacitor 28 operates while decreasing its output.
The voltage VC is increased by accumulating electric charges in the circuit. These operations are repeated, and each time the clamp pulse is output from the signal generation circuit 16 after the power is turned on, the capacitor 28 is charged.
The voltage VA at the output 102 of the amplifier 18 is
Approaching the voltage VR that occurs. When the voltage VA rises and exceeds the voltage Vcomp at the output 104 of the comparison voltage source 22, the comparator
20 switches from the signal Low, which has been output to the differential amplifier 24, to the signal Hi. When the signal Hi is output from the output 106 of the comparator 20, S2b of the switch S2 is connected to the contact S2c, and only the current I1 is supplied from the current source 30 to the transistor Q3.
Supplied to Q4. At this time, the clamp capacitor 28
The battery is charged by the charging current IX generated according to I1.
That is, the current IX that has been generated according to the currents I1 and I2 until now becomes a weak current generated according to the current I1. As described above, the differential amplifier 24, which has charged the clamp capacitor 28 with a large output current,
When VA becomes higher than the preset voltage Vcomp,
Since the voltage VC applied to the inverting input 110 of the amplifier 18 changes slowly, the output gradient of the output 102 becomes gentle as shown in FIG. 3 (t1).

When the clamp pulse goes low, the operation of the differential amplifier 24 is turned off, and the voltage of the inverting input 110 of the amplifier 18 is held by the voltage VC stored in the capacitor 28 until the next clamp pulse is generated. You. Or later,
When a clamp pulse is output from the signal generation circuit 16 at the interval 1H of the blanking period, the operation of the differential amplifier 24 is also turned on, and the capacitor 28 is charged by this clamp pulse. Therefore, as shown in FIG. 3E, the clamp circuit 12 adjusts the voltage of the output VA to a predetermined voltage Vc.
A differential amplifier that exceeds the omp and subsequently reduces the charging current
Soon after the storage of the capacitor 28 by the output of 24 is performed, the voltage VA becomes a steady state equal to the voltage VR, and the rising operation of the clamp circuit 12 is completed.

When the clamp circuit 12 enters the steady state, the reference level of the video signal during the blanking period is clamped by the clamp pulse output every blanking period, and the state where the voltage VA is equal to the voltage VR is maintained. . Therefore, when the shutter is released by the second release ON of the shutter button,
The video signal level during the clamp period is fixed to be the voltage VR, and the DC voltage VR is also added to the video signal other than during the clamp period, and the DC signal reproduced from the clamp circuit 12 is output. . The video signal whose reference level is clamped to a constant voltage irrespective of the magnitude of the luminance of the video signal is input to the video processing circuit 14 and is subjected to a predetermined video signal such as gamma correction, analog / digital conversion, or the like. The processing is performed accurately, and finally the data is stored in a storage medium such as a memory card.

Next, another embodiment in which the clamp circuit according to the present invention is applied to an electronic still camera will be described with reference to FIGS. In FIG. 4, the configuration of each circuit except for the clamp circuit 40 may be the same as the circuit of the embodiment shown in FIG.
Next, a functional configuration of the clamp circuit 40 will be described. The amplifier 18, the differential amplifier 24, the voltage supply 26, and the capacitor 28 of the clamp circuit 40 shown in FIG. 4 may have the same configuration as the embodiment of FIG. In addition, the clamp circuit 40 includes a charging circuit 42. The charging circuit 42 is a circuit that generates an output waveform based on the charged charging voltage and outputs a change in the voltage to an output 114. More specifically, the charging circuit 42 is a circuit that starts charging when power is supplied at time t0 as shown in FIG. 5 (B), and the voltage VJ of the output 114 increases every time the time elapses. At time t1, the charging circuit 42 changes the voltage VJ to the voltage Vcomp.
When time t1 elapses, the voltage VJ becomes the potential Vcomp
And is maintained at a constant voltage VJ. This output
Reference numeral 114 is connected to the non-inverting input (+) of the comparator 44.

The comparator 44 has an inverting input (-) 116 to which a comparison voltage source 46 for generating a comparison voltage Vcomp is connected, and switches the output which has determined the magnitude of the voltage of both inputs 114 and 116 to its output 118. A voltage determination circuit that generates a signal is configured. More specifically, the comparator 44 is configured as shown in FIG.
As shown in (B) and (C), the voltage VJ output from the charging circuit 42
Has a function to set the voltage of the output 118 to a low level when the voltage is lower than the voltage Vcomp, and to set the voltage of the output 118 to a high level when the voltage VJ is higher than the voltage Vcomp. The charging circuit 42, the comparator 44, and the comparison voltage source 46 constitute a timer circuit, and the output 118 is connected to the differential amplifier 24. Thus, the charging circuit 42, the comparator 44, the comparison voltage source 46, and the signal generating circuit 16 constitute a signal generating circuit that generates a signal for controlling the differential amplifier 24 to operate.

The operation of the clamp circuit according to this embodiment having the above configuration will be described below with reference to FIG. Referring to the figure, (A) shows the on / off state of the switch S1,
(B) is a change in the output voltage of the charging circuit 42, (C) is the output state of the comparator 42, (D) is the switching state of the current source of the differential amplifier 24, (E) is the output timing of the clamp pulse, (F) ) Indicates the voltage VA at the output node A of the amplifier 18, respectively. First, the first stroke of the shutter button is pressed, and in conjunction with this, the switch S1 is turned on (FIG. 5).
(A)), the ON state of the switch S1 is detected by the power supply circuit, and power is supplied to each unit. When power is supplied, the signal generation circuit 16 generates and outputs a clamp pulse (FIG. 5).
(E)).

When the power is turned on, the voltage VC of the inverting input 110 of the amplifier 18 is zero, and a video signal is input to the non-inverting input 100. Therefore, the voltage VA at the output 102 of the amplifier 18 increases. On the other hand, the charging circuit 42 starts charging when power is supplied, and the output 11 increases with time.
4 is applied to the non-inverting input 114 of the comparator 44. The inverting input 116 of the comparator 44 has a voltage source 46 for comparison.
During this period, the voltage VJ of the output 118 is lower than the voltage Vcomp as shown in FIG. 5C, and the comparator 44 outputs a low-level signal Low from the output 118 during this period. Output to the differential amplifier 24. This signal
When Low is input, the differential amplifier 24 connects S2b of the switch S2 to the contact S2a. As a result, as shown in FIG. 5D, currents I1 and I2 are supplied from the current source 30 and the additional current source 32 of the differential amplifier 24 to the transistor Q4. Thereafter, while the output 118 of the comparator 44 is at the low level, the differential amplifier 24
The operation of charging the capacitor 28 from is the same as the operation in the embodiment shown in FIG. 1 described above. Thus the amplifier 18
The voltage VA of the output 102 is the voltage of the output 108 of the reference voltage source 26.
Get closer to VR.

The charging circuit 42 is charged and the voltage VJ at the output 112 is
Exceeds the voltage Vcomp (t1 in FIG. 5B), the comparator 44 outputs the signal Lo that has been output to the differential amplifier circuit 24 up to that point.
Switch w to the high-level signal Hi. When this signal Hi is input, the differential amplifier 24 operates as S2b of the switch S2 shown in FIG.
To the contact S2c. To the Hi side. Thus, the differential amplifier 24 is supplied with the current I1 from the current source 30, and thereafter operates in the same manner as the embodiment shown in FIG. 1 to charge the capacitor 28 with a weak current. In this manner, when the power is supplied to the clamp circuit 40, the output of the differential amplifier circuit 24 is maintained until the voltage VJ reaches the preset voltage Vcomp as shown in FIGS. 5 (B) and 5 (F). When the voltage VJ exceeds the voltage Vcomp when the capacitor 28 is charged with a large charging current from 110, the capacitor 28 is charged with a weak charging current thereafter. Subsequent operations are the same as in the embodiment shown in FIG.

Next, another embodiment in which the clamp circuit according to the present invention is applied to an electronic still camera will be described with reference to FIG. In the figure, the configuration of each circuit except for the clamp circuit 50 may be the same as the circuit of the embodiment shown in FIG. Next, a functional configuration of the clamp circuit 50 will be described. This clamp circuit 50
Is a circuit in which the clamp circuit shown in FIG. 4 is realized by a hard clamp circuit. The comparator 51 of the clamp circuit 50 includes the charging circuit 42 and the comparator 44 shown in FIG.
The same functional configuration as that of the timer circuit including the comparison voltage source 46 may be used.

The clamp circuit 50 is a clamp capacitor
(C) 52, and the capacitor 52 is connected to the output of the signal input circuit 10.
100 is connected to one terminal, and the other terminal 120 is connected to the buffer 54 and the transistor Q11. The buffer 54 amplifies the video signal of the input 120 and outputs the amplified signal.
2 is the DC amplifier that outputs the signal. This output 122 constitutes the output of the clamp circuit 50. The input 120 is connected to the collector of the transistor Q11.
The base 124 and the emitter 126 are connected by a resistor (R) 56 for applying a bias therebetween. This emitter 12
6 is connected to a voltage source 58 that generates a voltage VR.
The transistor Q11 has a switch function of connecting the collector 120 and the emitter 126 according to the current flowing through the base 124, and a current control function of adjusting the charging current to the capacitor 52 according to the base current. This base 124
Is connected to a current source 60 for supplying a current I1. Further, the base 124 is connected to the contact S3a of the switch S3. The switch S3 switches the current I2 generated by the additional current source 62 to S3b.
Is a switching circuit for supplying the current I1 to the base 124 of the transistor Q11 in addition to the current I1. In addition, these current sources 60
The additional current source 62 generates a current in response to the clamp pulse supplied from the signal generating circuit 16, and supplies the generated current to the base 124 of the transistor Q11. On the other hand, the contact S3c of the switch S2 is grounded via the output line 126 to prevent the current I2 from being supplied to the base 124 of the transistor Q11.

These switching operations are performed by a switching signal output from the output 130 of the comparator 51 connected thereto. Specifically, the comparator 51 is configured as shown in FIG.
And a comparator 44 and a comparison voltage source 46. The output 130 outputs a low-level signal Low for a predetermined period to switch S3b of the switch S3 to the contact S3a. After a lapse of a predetermined period, a high-level signal Hi is output to switch S3b of the switch S3 to the contact S3.
Switch to c. The comparator 51 thus constitutes a timer circuit that outputs a switching signal. Thus, the comparator 51, the current source 60, the additional current source 62,
The switch S3 and the signal generation circuit 16 constitute a signal generation circuit that generates a signal for controlling the clamp operation.

The operation of the clamp circuit 50 according to this embodiment having the above configuration will be described below with reference to FIG.
Referring to the figure, (A) shows the on / off state of switch S1, (B) shows the output state of comparator 51, and (C) shows the switch state.
(D) shows the output timing of the clamp pulse, and (E) shows the voltage VA at the node A, respectively. First, when the first stroke of the shutter button is pressed and the switch S1 is turned on in conjunction with this,
(FIG. 7A), the ON state of the switch S1 is detected by the power supply circuit, and power is supplied to each unit. When power is supplied, the signal generation circuit 16 generates a clamp pulse and outputs the clamp pulse.
2 to the current source 60 and the additional current source 62. These current sources operate in synchronization with the clamp pulse.

On the other hand, the comparator 51 is internally charged after the power is turned on, and generates a low-level signal Low from its output 130 until the charged voltage reaches a predetermined voltage (see FIG. 4). 7 (B)), switch this signal Low
Output to S3. When a signal Low is input to the switch S3, S3b of the switch S3 is connected to the contact S3a (FIG. 7C),
A current I2 is applied to I1 and these are supplied to the base 124 and the resistor 56 of the transistor Q11. The collector current is adjusted according to the magnitude of the base current flowing through the base 124, and the potential VA at the node A approaches the voltage VR while the capacitor 52 stores the potential VA by the voltage VR biased to the emitter 126. In this way, power is stored in the capacitor 52 in synchronization with the clamp pulse.

When the time t1 has elapsed, the comparator 51 outputs a signal Hi from its output 130 as shown in FIGS. 7B and 7C, and switches the connection of the switch S3. Switch S3 S3b
Is connected to the contact S3c, a small current of only the current I1,
When the clamp pulse is generated, the clamp pulse is divided and supplied to the base 124 and the resistor 56 of the transistor Q11. At this time, since the transistor Q11 operates with the base current reduced as compared to before time t1, the collector current also decreases accordingly, and the capacitor 52 is charged with a smaller charging current than before time t1.

The signal transferred from the signal input circuit 10 is superimposed on the stored capacitor 52 and input to the buffer 54. This signal is amplified and output from the output 122, after which the clamp circuit 50 operates as in the embodiment shown in FIG.

As described above, in the embodiments of the present invention, the clamp capacitor is charged in a short time by increasing the charging current to the clamp capacitor after turning on the power in any of the embodiments. Thereafter, the charging current is relatively weakened and supplied to the clamp capacitor, so that the clamp capacitor is charged with a small charging current during the imaging operation. Therefore, after the power is turned on, the circuit is quickly brought into a steady state, and thereafter, the circuit is not charged with a large charging current, so that voltage fluctuation of a power source such as a battery can be prevented,
The power supply noise generated due to the voltage fluctuation can be reduced, and the noise mixed into the video signal can be minimized.

Although the differential amplifier 24, the current source 60 and the additional current source 62 shown in the embodiment operate in synchronization with the clamp pulse generated by the signal generation circuit 16, the present invention is not limited to this.
For example, when the clamp circuit rises with a large charging current, the signal generation circuit 16 generates a signal other than the clamp pulse to generate the differential amplifier 24, the current source 60 and the additional current source 62.
May be supplied and operated.

[0041]

As described above, according to the clamp circuit of the present invention, after the power is turned on, the clamp operation is performed with a large charge current, and thereafter the clamp operation is performed with a small charge current. The circuit can be started in a steady state, and after the steady state, the circuit is driven by a small charging current. As a result, it is possible to reduce the power supply noise generated due to the fluctuation of the power supply voltage at the time of the clamp operation in the steady state, and to prevent the noise from being mixed into the input signal and disturbing the signal. Therefore, as compared with the conventional high-speed clamp circuit, there is an excellent effect that a large current is not required in a steady state and the influence on other circuits such as a power supply can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of an electronic still camera to which a clamp circuit according to the present invention is applied.

FIG. 2 is a diagram showing an example of an internal configuration of a differential amplifier of the clamp circuit shown in FIG.

FIG. 3 is a timing chart showing an operation of each part of the clamp circuit shown in FIG. 1;

FIG. 4 is a diagram showing another embodiment of the electronic still camera to which the clamp circuit according to the present invention is applied.

FIG. 5 is a timing chart showing an operation of each unit of the embodiment of the clamp circuit shown in FIG. 4;

FIG. 6 is a diagram showing still another embodiment of the electronic still camera to which the clamp circuit according to the present invention is applied.

FIG. 7 is a timing chart showing an operation of each unit of the embodiment of the clamp circuit shown in FIG. 6;

[Explanation of symbols]

 S1 switch 12 Clamp circuit 16 Signal generation circuit (SSG) 18 Amplifier (AMP) 20 Comparator 22 Reference voltage source 24 Differential amplifier (FBC) 26 Reference voltage source 28 Clamp capacitor (C)

Claims (4)

(57) [Claims] 1. A clamp circuit for clamping a reference level of an input signal to a first reference voltage and outputting the clamped signal, the circuit comprising: a DC voltage applied to a control input and a voltage of the input signal. First amplifying means for amplifying a difference between the first differential amplifying means, voltage supply means for supplying a first reference voltage serving as a target of an output voltage output from the first differential amplifying means , A power storage means for applying a charging voltage to the control input of the differential amplifying means, and a clamp for clamping the input signal at predetermined intervals.
In response to a pump pulse, the output of the first differential amplifying means and an output corresponding to a difference between the first reference voltage and the power storage.
Feedback means for charging / discharging the means, and charging / discharging the power storage means.
Output current discharge and a variable feedback means, said feedback Hand
The stage outputs an output corresponding to a difference between the reference voltage and the output voltage.
A power supply means and a control input of the first differential amplifying means are provided.
A second differential amplifying means to be supplied and an output current of the second differential amplifying means to a supplied current.
Therefore, the current variable means to be controlled and the first current and the second current supplied to the current variable means
Current supply means for generating, upon receipt of the first current and second current, the current accepted
Switching means for switching the current supplied to the switching means, the switching means having a large value after turning on the power to the circuit.
Supplying a current to the current varying means, a first differential amplifying means;
When the output voltage of reaches a predetermined voltage,
To supply a small value current to the current variable means.
In other words, the second differential amplifying means is controlled by the current varying means.
A clamp circuit for supplying a controlled output current to the power storage means . 2. The clamp circuit according to claim 1 , wherein said circuit compares a first output voltage of a signal output from said first differential amplifier with a second reference voltage.
Comprises compare means, said switching means, after the power is turned on, the output voltage is the
Until the second reference voltage is reached, the large current is
Is supplied to the serial variable current means, is output voltage said second reference
After reaching the voltage , the small value current is
Clamp circuit according to claim and this is supplied to the stage. 3. The clamp circuit according to claim 1 , wherein the circuit is charged in accordance with a time after the power is turned on.
Timer means for performing output, the charge output and a third reference voltage
And a third comparing means for comparing the pressure with the pressure, wherein the switching means according to a comparison result of the third comparing means.
Until the charging output reaches the third reference voltage,
Supplying a large value current to the variable means,
After reaching the third reference voltage,
Clamp circuit according to claim and this supplied to the current changing means. 4. The clamp circuit according to claim 1, wherein
The circuit includes a pulse generator for generating the clamp pulse.
And a pulse generating means for supplying power to the circuit.
When the power is supplied, the clamp pulse is generated when the power is turned on.
And outputs the current to the current supply means.
Pump circuit.