JP3089021B2 - Sawtooth wave generator for vertical deflection - Google Patents

Description

The present invention relates to a vertical deflection saw-tooth wave generation circuit for a television receiver or the like, and more particularly to a method for displaying a plurality of video signals having different vertical frequencies. The present invention relates to a sawtooth wave generating circuit for vertical deflection suitable for a possible multi-system television receiver or the like.

(Prior Art) FIG. 3 is a circuit diagram showing a vertical deflection circuit employed in a television receiver. A portion surrounded by a broken line is a sawtooth wave generation circuit.

A saw-tooth wave generating circuit surrounded by a broken line is a reference voltage source V0 that generates a reference voltage V0, a switch S0 that is turned on and off by a vertical ramp pulse, a capacitor C0 having a capacitance of C0, and a constant current source that flows a constant current I0. It is composed of I0.

The error detection amplifier A1 is configured by a DC amplifier, and the inverting input terminal is connected to the output terminal of the capacitor C0. The output terminal of the error detection amplifier A1 is connected to one end of a deflection coil Dy via an amplifier A2, and the other end of the deflection coil Dy is connected to a reference potential point via a capacitor C1 and a feedback resistor R1. The connection point between the deflection coil Dy and the capacitor C1 is connected to the non-inverting input terminal of the error detection amplifier A1 via the resistor R2, and between the non-inverting input terminal and the connecting point of the capacitor C1 and the feedback resistor R1. The capacitor C2 is connected.

According to the above configuration, the switch S0 is turned on during the pulse period of the vertical ramp pulse (vertical synchronization separation pulse), and the capacitor C0 is charged by the reference voltage V0 during the ramp pulse period. The capacitor C0 discharges the charging electrification via the constant current source I0 during the non-pulse period. This charging / discharging generates a vertical period sawtooth voltage at the output terminal of the capacitor C0.
This sawtooth voltage is supplied to the inverting input terminal of the error detection amplifier A1. By controlling the discharge current of the capacitor C0 by the constant current source I0, a sawtooth voltage having good linearity can be obtained.

On the other hand, the current from the deflection coil Dy flows through the feedback resistor R1, and an AC signal due to the voltage drop of the feedback resistor R1 is supplied to the capacitor.
The signal is fed back to the non-inverting end of the error detection amplifier A1 via C2.
The error detection amplifier A1 outputs a signal to the amplifier A2 based on the error between the feedback signal from the resistor R2 and the sawtooth voltage waveform from the capacitor C0. This makes it possible to obtain a vertical sawtooth wave with even better linearity.

4 (a) and 4 (b) show the vertical ramp pulse and the sawtooth voltage generated at the output terminal of the capacitor C0, respectively.

As shown in FIG. 4 (b), the peak value of the sawtooth wave voltage is determined by the reference voltage V0, and the slope of the discharge period of the capacitor C0 can be expressed by the following equation (1).

Since the peak value of the sawtooth voltage is defined by the reference voltage V0, the amplitude of the sawtooth voltage is determined by the slope of the sawtooth voltage. That is, as shown in the above equation (1), the amplitude of the sawtooth voltage is determined by the constant current value I0. By making the constant current value I0 variable, the amplitude of the sawtooth voltage generated in the capacitor C0 can be changed, and the vertical amplitude of the screen can be adjusted.

By the way, broadcast systems in the world can be roughly classified into 50 Hz and 60 Hz in terms of vertical frequency. In the circuit of FIG. 3, when the vertical frequency changes, the amplitude of the vertical sawtooth waveform voltage from the capacitor C0 changes, and the vertical swing of the screen changes. Therefore, a multi-system television receiver capable of displaying two kinds of video signals having different vertical frequencies requires a means for keeping the vertical amplitude constant regardless of the vertical frequency.

FIG. 5 is a circuit diagram showing a conventional vertical deflection sawtooth wave generating circuit employed in a multi-system television receiver.

The vertical sawtooth voltage appearing on the capacitor C0 is supplied to an error detection amplifier A1 (not shown) (see FIG. 3).
It is also provided to one input terminal of the comparison amplifier A3. Comparison amplifier
The reference voltage Vr is applied to the other input terminal of A3, the output terminal is connected to the reference potential point via the capacitor Cx, and is connected to one input terminal of the voltage-current converter A4. The comparison amplifier A3 compares two inputs at the timing of the pulse for vertical amplitude comparison, and outputs an output based on a comparison error. The capacitor Cx holds this output until the next vertical amplitude comparison pulse period, and as a control voltage, the voltage-current converter A4
To one input terminal. A reference voltage Vx is supplied to the other input terminal of the voltage-current converter A4.
A4 flows a current based on the difference between the control voltage from the capacitor Cx and the reference voltage Vx. This current becomes the discharge current I of the capacitor C0.

FIG. 6 is a timing chart for explaining the operation of the conventional example of FIG. 6 (a) shows a vertical ramp pulse, FIG. 6 (b) shows a pulse for vertical amplitude comparison, FIG. 6 (c) shows a sawtooth voltage, and FIG. 6 (d).
Indicates a control voltage appearing on the capacitor Cx.

The vertical amplitude comparison pulse is generated immediately before the generation of the vertical ramp pulse, as shown in FIGS. 6 (a) and 6 (b). The comparison amplifier A3 compares the reference voltage Vr with the sawtooth voltage from the capacitor C0 during the pulse period of the vertical amplitude comparison pulse. That is, the comparison amplifier A3 compares the terminal voltage of the sawtooth voltage. This allows the comparison amplifier A3
Supplies a voltage corresponding to the error between the two voltages to the capacitor Cx. The control voltage held in the capacitor Cx is supplied to the voltage-current converter A4 and compared with the reference voltage Vx. Voltage-
The current converter A4 converts the current based on the difference between the two voltages into a capacitor.
It flows as the discharge current I of C0. That is, the discharge current I of the capacitor C0 is based on the voltage value at the end of the vertical period of the sawtooth wave.

For example, the sawtooth voltage at the end of the vertical period is the reference voltage Vr
, The control voltage of the capacitor Cx increases (solid line in FIG. 6D), and the current I flowing through the current converter A4 increases. As a result, the amplitude of the sawtooth voltage of the capacitor C0 increases. Conversely, if the sawtooth voltage at the end of the vertical period is smaller than the reference voltage Vr, the capacitor
The control voltage of Cx decreases (broken line in FIG. 6D), and the current I flowing through the voltage-current converter A4 decreases. Then, the amplitude of the sawtooth voltage becomes smaller.

In this way, the discharge current of the capacitor C0 is automatically adjusted to obtain a sawtooth wave for vertical deflection having substantially the same amplitude regardless of the vertical frequency.

By the way, in a video tape recorder, when the still mode is designated, the vertical cycle may be different for each field. Also, a video signal output from an electronic still camera or the like may have a different vertical cycle for each field. When such a video signal is input to the television receiver, there is a problem that image blur occurs at the lower side of the screen.

FIG. 7 is a timing chart for explaining this problem. FIGS. 7 (a) to (d) correspond to FIGS. 6 (a) to (d), respectively. Note that T1 indicates a first field period, and T2 indicates a second field period.

As shown in FIG. 7 (a), the interval T1 between the vertical ramp pulses in the first field and the interval T2 between the vertical ramp pulses in the second field are different, the first field period T1 is relatively long, The period T2 is relatively short. Since the discharging time of the capacitor C0 is long in the first field period T1, the sawtooth voltage value in the vertical amplitude comparison pulse period at the end of the period T1 is lower than the reference voltage Vr (FIGS. 7B and 7C). ). Then, in the vertical amplitude comparison pulse period, as shown in FIG. 7D, the control voltage of the capacitor Cx decreases. As a result, the discharge current I flowing through the voltage-current converter A4 decreases. The control voltage of the capacitor Cx is held until the next vertical amplitude comparison pulse period, and eventually, in the next second field period T2, as shown in FIG.
The slope of the sawtooth voltage decreases.

Conversely, in the second field period, the period T2 is the period
As described above, since the discharge current I is small during this period, the amplitude of the sawtooth voltage is small, and the sawtooth voltage value during the vertical amplitude comparison pulse period is higher than the reference voltage Vr. . Therefore, as shown in FIG. 7 (d), the control voltage of the capacitor Cx increases during the amplitude comparison pulse period, and the discharge current I during the next first field period T1 is increased.
Becomes larger.

Originally, the capacitor C0
To reduce the slope of the sawtooth wave,
It is necessary to suppress the amplitude from increasing, and it is necessary to suppress the decrease in the amplitude by increasing the discharge current I of the capacitor C0 in the short second field period.
However, as described above, in the circuit of FIG. 5, the slope of the sawtooth wave voltage during the first field period is large,
The slope of the sawtooth voltage during the field period is small. That is, in the first field having a long vertical cycle, the vertical amplitude is further increased, and in the second field having a short vertical cycle, the vertical amplitude is further reduced. The difference between the vertical amplitudes of the first and second fields causes a blur on the lower side of both surfaces.

Therefore, for example, by increasing the capacitance value of the capacitor Cx, it is conceivable to reduce the fluctuation of the slope of the vertical sawtooth wave with respect to the fluctuation of the input vertical cycle and to keep the vertical amplitude constant. However, in this case, there is a disadvantage that it takes a long time until the vertical screen size becomes a normal size when switching the image receiving channel or the like.

(Problems to be Solved by the Invention) As described above, in the above-described conventional vertical deflection sawtooth wave generating circuit, when the vertical period changes between the first field and the second field, the vertical amplitude is large. There is a problem in that the image fluctuates and blur occurs on the lower side of the screen.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a vertical deflection saw-tooth wave generation circuit that can reduce screen shake even when the field period changes.

[Structure of the Invention] (Means for solving the problem) A sawtooth wave generating circuit for vertical deflection according to claim 1 of the present invention repeats charging and discharging in a vertical cycle to generate a sawtooth wave in a vertical cycle. A sawtooth wave generating circuit having: a comparison means for comparing a voltage at the end of a vertical period of the sawtooth wave with a predetermined reference voltage, amplifying a comparison error with a predetermined gain, and outputting the result; Holding means for holding an output, a voltage-current converter for determining a charge or discharge current amount of the capacitor based on an output from the holding means,
For controlling the gain of the comparing means, when the vertical synchronization is taken, reduce the gain of the comparing means,
A gain control means for increasing the gain of the comparing means when the signal is asynchronous.

(Operation) In the present invention, the sawtooth wave generated in the capacitor is compared with a predetermined reference voltage by the comparing means in the period of the vertical period. The comparing means amplifies the comparison error between the two with a predetermined gain and outputs the result. An output based on the amplitude of the sawtooth wave is output from the comparing means, and this output is held by the holding means until the end of the next vertical period. The voltage-current converter determines the amount of charge or discharge current of the capacitor based on the output of the holding means. Thus, the amount of charge or discharge current of the capacitor is controlled based on the amplitude of the sawtooth wave, and the amplitude of the sawtooth wave becomes constant. Further, when the vertical synchronization is established, the gain control means reduces the gain of the comparison means. Thus, the change in the output of the comparison means is relatively small with respect to the change in the amplitude of the sawtooth wave, and even when the vertical period changes for each field and the amplitude of the sawtooth wave changes,
The change in the amplitude of the sawtooth wave is small. When the vertical synchronization is not established, the gain of the comparing means is large, and the change of the output of the comparing means is large with respect to the change of the vertical amplitude. Therefore, the amplitude of the sawtooth wave reaches a predetermined magnitude in a short time.

(Example) Hereinafter, an example of the present invention is described with reference to drawings. FIG. 1 is a circuit diagram showing an embodiment of a sawtooth wave generating circuit for vertical deflection according to the present invention. In FIG. 1, the same components as those in FIG. 5 are denoted by the same reference numerals.

One end of the capacitor C0 is connected to the reference potential point,
The output terminal is supplied with the reference voltage V0 via the switch S0. The switch S0 is turned on during the pulse period of the vertical ramp pulse. The output terminal of the capacitor C0 is connected to the output terminal 1 and has a voltage −
It is also connected to the output terminal of the current converter A4.

The discharge current I of the capacitor C0 is determined by the variable gain comparator A5, the reference voltages Vr, Vx, the capacitor Cx, and the voltage-current converter A4.
Is controlled by the That is, the sawtooth voltage appearing at the output terminal of the capacitor C0 is supplied to the output terminal 1 and also to one input terminal of the variable gain comparison circuit A5. The reference voltage Vr is applied to the other input terminal of the variable gain comparison circuit A5. The variable gain comparison circuit A5 compares the two inputs during the pulse period of the vertical amplitude comparison pulse, and converts the comparison error into a gain switching control signal. It amplifies with the gain based on and outputs. The output terminal of the variable gain comparison circuit A5 is connected to the reference potential point via the capacitor Cx, and is connected to one input terminal of the voltage-current converter A4. A reference voltage Vx is supplied to the other input terminal of the voltage-current converter A4, and the voltage-current converter A4 flows a current based on a difference between two inputs as a discharge current I.

FIG. 2 is a circuit diagram showing a specific configuration of the variable gain comparison circuit A5.

The sawtooth voltage supplied from the capacitor C0 via the input terminal 2 is applied to the base of the transistor Q5. The transistor Q5 has a collector connected to the reference potential point and an emitter connected to the base of the transistor Q6. The transistor Q6 forms a differential amplifier together with the transistor Q7, the collector is connected to the collector and the base of the transistor Q9, and the common emitter is connected to the collector of the transistor Q4. The collector of transistor Q7 is a transistor
Connected to the collector of Q10, the base is connected to the emitter of transistor Q8. The emitters of the transistors Q9 and Q10 are both connected to the reference potential point.
A current mirror circuit is formed by Q9 and Q10. The transistor Q8 forms a differential pair with the transistor Q5, the collector is connected to the reference potential point, and the reference voltage Vr is applied to the base. These transistors Q5 to Q10 form a comparison circuit, and the output of this comparison circuit is supplied to the capacitor Cx from the collector of the transistor Q7.

The emitter of transistor Q4 is connected to power supply terminal 3,
The base is connected to the base and the collector of the transistor Q3. The emitter of the transistor Q3 is connected to the power supply terminal 3, and the transistors Q3 and Q4 form a current mirror circuit. The collector of the transistor Q3 is connected to the reference potential point via the collector-emitter path of the transistor Q2 and the resistor R3. The emitter of the transistor Q2 is also connected to the reference potential point via the resistor R4 and the collector-emitter path of the transistor Q1, and a pulse for vertical amplitude comparison is applied to the base via the terminal 4. A gain switching control signal is supplied to the base of the transistor Q1 via the terminal 5.

The sawtooth voltage from the capacitor C0 is changed to the reference voltage by the comparison circuit constituted by the transistors Q5 to Q10.
Compared to Vr. Here, during a period other than the pulse period of the vertical amplitude pulse, the transistor Q2 is off, no current flows through the emitter-collector paths of the transistors Q3 and Q4, and no output of the comparison circuit is generated. During the pulse period of the vertical amplitude comparison pulse, the transistor Q2 is on, and the gain based on the current flowing through the common emitter of the transistors Q6 and Q7 is output from the collector of the current transistor Q7 according to the error voltage.

The current flowing through the common emitter of the transistors Q6 and Q7 is controlled by a gain switching control signal. For example, when a high level (hereinafter, referred to as “H”) gain switching control signal is input via the terminal 5, the transistor Q1 turns on,
The resistor R4 is connected in parallel with the resistor R3. On the other hand, the transistor Q1 is turned off by the low level (hereinafter, referred to as "L") gain switching control signal, and only the resistor R3 is connected between the emitter of the transistor Q2 and the reference potential point. That is, the collector current of the transistor Q2 is increased by the gain switching control signal of "H", and the transistors Q6 and Q7 are switched by the current mirror circuit including the transistors Q3 and Q4.
Also increase the common emitter current. Conversely, the "L" gain switching control signal reduces the collector current of transistor Q2 and the common emitter current of transistors Q6 and Q7.

Suppose now that the common emitter current of the transistors Q6 and Q7 is I1, the sawtooth voltage of the base of the transistor Q5 and the reference voltage.
Assuming that an error voltage from Vr is ΔV and an output current from the collector of the transistor Q7 is Iout, the output current Iout is expressed by the following equation (2).

Here, k is Boltzmann's constant and q is Coulomb charge.

As shown in the equation (2), the gain of the comparison circuit is proportional to the common emitter current 11. Therefore, the gain of the comparison circuit is increased by the "H" gain switching control signal, and the gain of the comparison circuit is decreased by the "L" gain switching control signal.

The gain switching control signal exhibits “L” when a vertical synchronization circuit (not shown) is synchronized with the vertical synchronization signal of the input video signal, and the vertical synchronization circuit is asynchronous with the vertical synchronization signal of the input video signal. Alternatively, if the price is synchronized, "H" is presented.

Next, the operation of the thus configured vertical deflection sawtooth wave generation circuit will be described.

The switch S0 is turned on during the pulse period of the vertical ramp pulse, and the capacitor C0 is charged to the reference voltage V0. When the ramp pulse period ends, the charge stored in the capacitor C0 is discharged via the voltage-current converter A4. At the end of the discharge, that is, immediately before the pulse period of the vertical ramp pulse, the pulse period for vertical amplitude comparison is started. Then, the transistor Q2 is turned on, and the saw-tooth waveform voltage from the capacitor C0 is compared with the reference voltage Vr in the comparison circuit including the transistors Q5 to Q10.

Now, when the gain switching control signal is "L" with vertical synchronization, the transistor Q1 is off and the collector current value of the transistor Q2 is relatively small. For this reason, the common emitter current I1 of the transistors Q6 and Q7 is also small, and the comparison circuit amplifies the error voltage between the sawtooth voltage and the reference voltage Vr with a relatively small gain and supplies the amplified voltage from the collector of the transistor Q7 to the capacitor Cx. The control voltage from the capacitor Cx is compared with the reference voltage Vx in the voltage-current converter A4, and a current based on the error flows from the capacitor C0 through the voltage-current converter A4.

Since the gain of the comparison circuit is small, the change of the control voltage appearing on the capacitor Cx is small. Therefore, as shown in FIG. 7, even when the vertical cycle differs between the first field and the second field, the change in the discharge current I of the capacitor C0 is small, and the fluctuation amount of the vertical amplitude for each field is small. As a result, it is possible to reduce screen shake.

On the other hand, when vertical synchronization is not established and the gain switching control signal is "H", such as when switching channels, the transistor Q1 is on and the resistors R3 and R4 are connected in parallel. Therefore, the collector current of transistor Q2 is relatively large, and the common emitter current of transistors Q6 and Q7 is large. That is, the gain of the comparison circuit is large and the capacitor Cx
, A control voltage that greatly changes in accordance with the change in the voltage at the end of the sawtooth wave appears. Therefore, the amount of change in the discharge current I of the capacitor C0 is large, and the amplitude of the sawtooth voltage reaches the predetermined value in a short period. Thereby, the vertical amplitude of the screen is stabilized in a short period.

As described above, in the present embodiment, when the vertical synchronization is achieved, the gain of the variable gain comparison circuit A5 is reduced to reduce the variation of the vertical amplitude for each field.
The screen shake is suppressed, and when vertical synchronization is not achieved, the gain of the gain possible comparison circuit A5 is increased so that the screen size becomes a predetermined size in a short period of time.

[Effects of the Invention] As described above, according to the present invention, the gain of the comparing means is controlled by the gain control means, so that even if the field period changes, it is possible to reduce the blur of the screen. Have.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a sawtooth wave generating circuit for vertical deflection according to the present invention, FIG. 2 is a circuit diagram showing a specific configuration of a variable gain comparison circuit A5 in FIG. 3 is a circuit diagram showing a vertical deflection circuit, FIG. 4 is a timing chart for explaining the operation of FIG. 3, FIG. 5 is a circuit diagram showing a conventional vertical deflection sawtooth wave generation circuit, and FIG. 7 is a timing chart for explaining the operation of the conventional example, and FIG. 7 is a timing chart for explaining the problems of the conventional example. C0, Cx: Capacitor, A5: Variable gain comparison circuit, Vr, Vx: Reference voltage source, A4: Voltage-current converter.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-131716 (JP, A) JP-A-64-97661 (JP, A) JP-A-62-98976 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N 3/16 H03K 4/501 H04N 3/22 H04N 3/27

Claims (2)

(57) [Claims] A sawtooth wave generating circuit having a capacitor for repeating charge and discharge in a vertical cycle to generate a sawtooth wave of a vertical cycle; and a voltage at the end of a vertical period of the sawtooth wave and a predetermined reference voltage. Comparing means for comparing and amplifying and outputting a comparison error with a predetermined gain; holding means for holding an output of the comparing means; and determining a charge or discharge current amount of the capacitor based on an output from the holding means. A voltage-current converter for controlling the gain of the comparing means, and when the vertical synchronization is achieved, reduce the gain of the comparing means;
And a gain control means for increasing the gain of the comparing means when the signal is asynchronous. 2. The comparing means supplies first and second transistors, each having an emitter connected to a common current source, and the vertical period sawtooth voltage to the base of the first transistor, Means for supplying the reference voltage to the base of the second transistor, wherein the gain control means switches the current flowing through the current source during the comparison period of the comparing means by the gain switching control signal. The sawtooth wave generating circuit for vertical deflection according to claim 1, wherein: