JP6014224B2 - Clamp circuit, semiconductor device, signal processing system, and signal clamp method - Google Patents

Description

  The present invention relates to a clamp circuit, a semiconductor device, a signal processing system, and a signal clamping method, and more particularly to a clamp circuit, a semiconductor device, a signal processing system, and a signal clamping method for clamping a video signal.

  In general, a clamp circuit used in an analog front end that processes a video signal as a signal is known. The clamp circuit has a function of adding a direct current component to a video signal waveform and fixing a predetermined portion of the waveform to a constant voltage, and is composed of an input capacitor, a constant current source, and a comparator. A comparator compares an arbitrary reference voltage with a terminal voltage, and when the terminal voltage is lower, a constant current source is connected to the input capacity to charge the input capacity.

  FIG. 2 shows an example of a video signal. The video signal includes a synchronization signal, a burst signal, and a video signal. When the video signal of FIG. 2 is input, the clamp circuit charges and clamps so that the synchronization signal having the lowest voltage is equal to the reference voltage. When the synchronization signal level reaches the reference voltage, a normal image signal is output. An example of such a clamp circuit is Patent Document 1.

  FIG. 20 shows a basic clamp circuit configuration. The clamp circuit 1030 illustrated in FIG. 20 includes a comparator, a clamp current source, and a control switch.

  The operation of the clamp circuit 1030 shown in FIG. 20 will be described. The control switch connects the input terminal and the clamp current source, and supplies current to the input capacitor when the switch is on. The comparator compares the input terminal voltage with the reference voltage, and turns the switch on when the input terminal voltage is lower. On the other hand, when the input terminal voltage is higher, the switch is turned off.

  However, in this method, when the input terminal voltage in the synchronization period is lower than the reference voltage and the input terminal voltage in the burst signal or video signal period other than the synchronization period is higher than the reference voltage, charging is performed only in the synchronization period, and other periods Is not charged. For example, an NTSC (National Television Standards Committee) video signal used in Japan or the like has a horizontal synchronization signal period of 63.5 μs and a synchronization period of about 4.5 μs. 0.5 μs / 63.5 μs = 7.1%, and the charging period per cycle is short. Therefore, many cycles are required until the charging is completed, and as a result, there is a problem that the charging time (the time from the start of charging to the completion of charging) becomes long.

  To solve this problem, the charging time can be shortened by reducing the input capacity.

  Further, the charging time can be shortened by increasing the clamp current (current supplied for charging the input capacitance) (see, for example, Patent Document 2).

JP 2011-4071 A JP 05-292345 A

  However, when the charging time is shortened by reducing the input capacity, the input terminal sag (fluctuation) increases at the time of clamping and the stability of the input terminal voltage against noise decreases when the input capacity decreases. Problems arise.

  In addition, when the charging time is shortened by increasing the clamp current as in the technique described in Patent Document 2, the clamp current flows to the outside of the signal source, so that a voltage drop occurs with respect to the signal source impedance. . This voltage drop pushes up the input terminal voltage, and at the moment when the clamp current stops flowing, the voltage drop disappears and the signal source potential changes, and at the same time, the input terminal voltage changes. When the clamp current is large, this potential change is large, which causes a problem that an error between the synchronization signal level and the target clamp voltage becomes large.

  The present invention has been proposed to solve the above-described problems, and shortens the charging time required for charging the clamp capacitor without reducing the clamp capacitor and without increasing the clamp current required for charging. An object of the present invention is to provide a clamping circuit, a semiconductor device, a signal processing system, and a signal clamping method.

  In order to achieve the above object, a clamp circuit of the present invention includes a first switching element disposed between a first capacitor to which a signal is input and a current supply source, the current supply source, and the first supply source. A second switching element disposed between the capacitor, a first control unit that connects the first switching element when the signal is in a synchronization period, and a burst period in which the signal is in the synchronization period And a second control unit for connecting the second switching element.

  The semiconductor device of the present invention includes a first terminal electrically connected to a first capacitor to which a signal is input, a second terminal electrically connected to a current supply source, the first capacitor, and the first capacitor. A first switching element disposed between a current supply source, a second switching element disposed between the current supply source and the first capacitor, and the signal is in a synchronization period, A first control unit that connects the first switching element; and a second control unit that connects the second switching element when the signal is in a synchronous period and a burst period.

  The signal processing system of the present invention includes a first capacitor to which a signal is input, a first terminal electrically connected to the first capacitor, a current supply source, and an electrical connection to the current supply source. A second terminal, a first switching element disposed between the first capacitor and the current supply source, and a second switching disposed between the current supply source and the first capacitor. A first control unit that connects the first switching element when the signal is in a synchronization period, and the second switching element is connected when the signal is in a synchronization period and a burst period A second control unit.

   According to the signal clamping method of the present invention, when the signal input to the first capacitor is in the synchronization period, the first switching element disposed between the first capacitor and the current supply source is connected to the first control unit. And a first control step for connecting a second switching element disposed between the current supply source and the first capacitor when the signal is in a synchronous period and in a burst period. 2 control steps.

  According to the present invention, there is an effect that the charging time required for charging the clamp capacitor can be shortened without reducing the clamp capacity and without increasing the clamp current required for charging.

It is a schematic structure figure showing an example of a schematic structure of a signal processing system provided with a clamp circuit concerning a 1st embodiment. It is explanatory drawing which shows a specific example of the video signal processed with the signal processing system which concerns on 1st Embodiment. It is a circuit diagram which shows a specific example of the clamp circuit which concerns on 1st Embodiment. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 1st Embodiment is incomplete. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 1st Embodiment is incomplete. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 1st Embodiment is completed. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 1st Embodiment is completed. It is a schematic block diagram which shows an example of schematic structure of the signal processing system provided with the clamp circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows a specific example of the clamp circuit which concerns on 2nd Embodiment. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 2nd Embodiment is incomplete. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 2nd Embodiment is incomplete. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 2nd Embodiment is completed. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 2nd Embodiment is completed. It is a schematic block diagram which shows an example of schematic structure of the signal processing system provided with the clamp circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows a specific example of the clamp circuit which concerns on 3rd Embodiment. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 3rd Embodiment is incomplete. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 3rd Embodiment is incomplete. It is a flowchart which shows an example of the flow of the clamp operation | movement in a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 3rd Embodiment is completed. It is explanatory drawing which shows an example of each node voltage of a clamp circuit when charge of the input capacity | capacitance C1 which concerns on 3rd Embodiment is completed. It is a circuit diagram which shows a specific example of the conventional clamp circuit.

  [First Embodiment]

  Hereinafter, a clamp circuit according to a first embodiment of the present invention and a signal processing system of an LSI (semiconductor integrated circuit: semiconductor device) including the clamp circuit will be described in detail with reference to the drawings.

  First, the configuration of the signal processing system according to the present embodiment will be described. An example of a schematic configuration of the signal processing system according to the present embodiment is shown in FIG. The signal processing system 10 of the present embodiment shown in FIG. 1 clamps an input capacitor C1 to which a video signal is input from a signal source via a node N1, and a signal input from the input capacitor C1 via a node N2. A clamp circuit 30 (to be described later in detail), a clamp reference voltage to the node N3 of the clamp circuit 30, and a reference voltage source 24 to supply a reference voltage to the node N6, and a clamped signal input via the node N2 The next-stage circuit 26 that performs predetermined video processing is provided with the LSI 20 formed on the same substrate 22.

  A specific example of a video signal processed by the signal processing system 10 of this embodiment is shown in FIG. The video signal is a composite video signal, and as shown in FIG. 2, one cycle is composed of a plurality of cycles including a synchronization signal (synchronization period), a burst signal (burst signal period), and a video signal (video signal period). Signal. The synchronization signal is a signal for determining the scanning position and timing, and the burst signal is a signal serving as a reference for the hue.

  FIG. 3 shows a circuit diagram of a specific example of the clamp circuit 30 of the present embodiment. The clamp circuit 30 of the present embodiment has a function of adding a DC component of the video signal to the video signal, and fixes the bottom of the synchronization signal to the clamp reference voltage. The clamp circuit 30 includes a switching circuit 34 that connects a node N0 to which a current source I1 that supplies a charging clamp current to the input capacitor C1 and a node N2, a first control circuit 32, and a second control circuit. And a circuit 36.

  The switching circuit 34 includes a switching element SW1 and a switching element SW2. The first control circuit 32 compares the clamp reference voltage input to the node N3 (hereinafter referred to as clamp reference voltage V (N3)) with the signal voltage at the node N2 (hereinafter referred to as voltage V (N2)). A comparator X1 is provided that outputs a control signal (switching element SW1 is turned on by a signal at H level) to the control node N4 so as to turn on the switching element SW1 of the switching circuit 34 when the clamp reference voltage is higher. Has been. On the other hand, the second control circuit 36 includes a capacitor C2 that connects between the control node N5 that outputs a control signal for controlling the switching element SW2 (the switching element SW2 is turned on by an H level signal) and the ground potential Vss; A resistor R1 connected in parallel with the capacitor C2, a switching element SW3 connecting the power supply potential Vdd and the control node N5, a reference voltage (hereinafter referred to as reference voltage V (N6)) input to the node N6, and a node N2 And a comparator X2 that outputs a control signal (the switching element SW3 is turned on by a signal at the H level) to the control node N7 so as to turn on the switching element SW3 when the reference voltage is higher. , And is configured. In the present embodiment, the reference voltage is set to a voltage whose voltage value is smaller than the clamp reference voltage (details will be described later).

  Next, the clamp operation by the clamp circuit 30 of this embodiment and the voltage of each node (including the control node) will be described.

  First, the clamp operation and each node voltage when the input capacitor C1 is not fully charged will be described. FIG. 4 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 30 when the charging of the input capacitor C1 is not completed. FIG. 5 shows an example of each node voltage of the clamp circuit 30.

  As shown in FIG. 5, when the charging of the input capacitor C1 is not completed, the voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6 and after the synchronization period ends. The voltage V (N2) at the node N2 during the burst signal period and the video signal period is higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 30 will be described. The comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 4: step 100). During the synchronization period, since the clamp reference voltage V (N3) is equal to or higher than the voltage V (N2) of the node N2 (FIG. 4: step 102), an H level control signal is output from the comparator X1 to the control node N4. SW1 is turned on (FIG. 4: step 104, FIG. 5: timing t1a).

  On the other hand, the operation of the second control circuit 36 of the clamp circuit 30 will be described. The comparator X2 compares the reference voltage V (N6) at the node N6 with the voltage V (N2) at the node N2 (FIG. 4: step 200). During the synchronization period, since the reference voltage V (N6) is equal to or higher than the voltage V (N2) of the node N2 (FIG. 4: step 202), an H level control signal is output from the comparator X2 to the control node N7, and the switching element SW3 Is turned on (FIG. 4: step 204, FIG. 5: timing t1a).

  When the switching element SW3 is turned on, in the second control circuit 36, the power supply potential Vdd and the capacitor C2 are connected, and the capacitor C2 is charged. Further, the voltage V (N5) of the control node N5 is output as a control signal to the switching element SW2 of the switching circuit 34 (FIG. 4: step 206, FIG. 5: timing t1a).

  In the clamp circuit 30 of the present embodiment, as a specific example, MOS (Metal-Oxide-Semiconductor Field Effect Transistor) transistors are used as the switching elements SW1, SW2, and SW3, and the voltage V (N5) of the control node N5 is used. Until the threshold voltage Vt of the MOS transistor is exceeded, the switching element SW2 is kept off (FIG. 4: negative in step 208, FIG. 5: period from timing t1a to t2a). When the voltage V (N5) of the control node N5 exceeds the threshold voltage Vt of the MOS transistor (FIG. 4: affirmative in step 208, FIG. 5: timing t2a), the switching element SW2 is turned on (FIG. 4: step 210, FIG. 5: Timing t2a).

  Thus, the switching element SW1 controlled by the first control circuit 32 is turned on at the timing t1a, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. At the timing t2a, the switching element SW2 controlled by the second control circuit 36 is also turned on, and the input capacitor C1 is charged by the current I1 supplied from the current source I1.

  During the synchronization period of the video signal, voltage V (N2) of node N2 <reference voltage V (N6) <clamp reference voltage V (N3) (FIG. 4: positive at step 106 and positive at step 212, FIG. During the period from timing t1a to t3a), the voltage V (N4) of the control node N4 and the voltage V (N5) of the control node N5 become H level, and the switching element SW1 and the switching element SW2 of the switching circuit 34 are turned on. The input capacitor C1 is charged by the current I1 supplied from the current source I1.

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 5: timing t3a), the reference voltage V (N6) <the clamp reference voltage V (N3) <the voltage V (N2) of the node N2 (FIG. 4: negative in step 106 and negative in step 212), the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 4: step 108, FIG. 5: timing t3a).

  On the other hand, in the second control circuit 36, the comparator X2 outputs an L level control signal to the control node N7. As a result, the switching element SW3 is turned off (FIG. 4: step 214, FIG. 5: timing t3a). When the switching element SW3 is turned off, the electric charges of both electrodes of the capacitor C2 are discharged by the resistor R1 (FIG. 4: step 216). Due to the discharge of the capacitor C2, the voltage V (N5) of the control node N5 is changed from the H level to the ground potential Vss for a predetermined time (for example, a time obtained in advance based on the amount of charge accumulated in the capacitor C2). Transition. Here, when the voltage V (N5) of the control node N5 is equal to or higher than the threshold voltage Vt of the switching element SW2 (FIG. 4: affirmative in Step 218), the switching element SW2 is kept on and supplied from the current source I1. The input capacitor C1 is charged by the current I1. On the other hand, when the voltage V (N5) of the control node N5 becomes less than the threshold voltage Vt of the switching element SW2 (FIG. 4: negative in step 218, FIG. 5: timing t4a), the switching element SW2 is in an off state (FIG. 4: Step 220), and no current is supplied from the current source I1 to the node N2, so that the charging of the input capacitor C1 is stopped.

  Next, a clamp operation and each node voltage when the input capacitor C1 has been charged will be described. FIG. 6 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 30 when the charging of the input capacitor C1 is completed. FIG. 7 shows an example of each node voltage of the clamp circuit 30.

  As shown in FIG. 7, when the charging of the input capacitor C1 is completed, the voltage V (N2) of the node N2 in the synchronization period is higher than the reference voltage V (N6) of the node N6, and the clamp of the node N3 The voltage V (N2) at the node N2 in the burst signal period and the video signal period after the end of the synchronization period is lower than the reference voltage V (N3) and higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 30 will be described. The comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 6: step 150). During the synchronization period, since the clamp reference voltage V (N3) is equal to or higher than the voltage V (N2) of the node N2 (FIG. 6: step 152), an H level control signal is output from the comparator X1 to the control node N4. SW1 is turned on (FIG. 6: step 154, FIG. 7: timing t1b).

  On the other hand, the operation of the second control circuit 36 of the clamp circuit 30 will be described. The comparator X2 compares the reference voltage V (N6) at the node N6 with the voltage V (N2) at the node N2 (FIG. 6: step 250). Since the reference voltage V (N6) is smaller than the voltage V (N2) of the node N2 in the state where the charging of the input capacitor C1 is completed (FIG. 6: step 252), the L level is output from the comparator X2 to the control node N7. A control signal is output, and the switching element SW3 is kept off (FIG. 6: step 254, FIG. 7: timing t1b).

  Since the switching element SW3 is in the OFF state, the voltage V (N5) of the control node N5 output to the switching element SW2 of the switching circuit 34 maintains the L level (FIG. 6: step 256), and therefore the switching element SW2 (FIG. 6: step 258, FIG. 7: timing t1b).

  Thus, the switching element SW1 controlled by the first control circuit 32 is turned on at the timing t1b, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. On the other hand, the switching element SW2 controlled by the second control circuit 36 maintains the off state. However, when the switching element SW1 is on, the input capacitor C1 is charged by the current I1 supplied from the current source I1. The

  Since the reference voltage V (N6) <the voltage V (N2) of the node N2 <the clamp reference voltage V (N3) during the synchronization period of the video signal (FIG. 6: positive in step 156, FIG. 7: timings t1b to t2b) ), The voltage V (N4) of the control node N4 becomes H level, the voltage V (N5) of the control node N5 becomes L level, the switching element SW1 of the switching circuit 34 is turned on, and the switching element SW2 is turned off. Hold. Thereby, the input capacitor C1 is charged by the current I1 supplied from the current source I1.

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 7: timing t2b), reference voltage V (N6) <clamp reference voltage V (N3) <voltage V (N2) of node N2 (FIG. 6: negative in step 156), the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 6: step 158, FIG. 6: timing t2b).

  On the other hand, in the second control circuit 36, since the control node N7 holds the L level control signal, the switching element SW3 holds the OFF state, and the switching element SW2 also holds the OFF state (FIG. 6: step 258, FIG. 7: Timing t2b-).

  Thus, during the burst signal period and the video signal period, since both the switching element SW1 and the switching element SW2 of the switching circuit 34 are in the off state, the current I1 is not supplied from the current source I1, and the input capacitor C1 is not charged.

  As described above, the clamp circuit 30 in the semiconductor device 20 of the signal processing system 10 according to the present embodiment includes the first control circuit 32, the switching circuit 34, and the second control circuit 36. The switching circuit 34 includes a switching element SW1 and a switching element SW2 that are connected in parallel and turned on by an H level control signal between the current source I1 and the node N2 (input capacitance C1). The first control circuit 32 includes a comparator X1, compares the voltage V (N2) of the node N2 with the clamp reference voltage V (N3) of the node N3, and voltage V (N2) ≦ clamp reference voltage V In the case of (N3), an H level control signal is output to the control node N4. The second control circuit 36 connects the comparator X2, the capacitor C2 having one end connected to the ground potential Vss, the resistor R1 connected in parallel with the capacitor C2, and the other end of the capacitor C2 and the power supply potential Vdd. And a switching element SW3 which is turned on by an H level control signal. The comparator X2 compares the voltage V (N2) at the node N2 with the reference voltage V (N6) at the node N6, and if the voltage V (N2) ≦ the reference voltage V (N6), the comparator X2 supplies the control node N7 with H. A level control signal is output. Further, a signal voltage at an intermediate node between the switching element SW3 and the capacitor C2 is output as a control signal to the control node N5.

  The voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6, and the voltage V (N2) of the node N2 in the burst signal period and the video signal period after the synchronization period ends When charging of the input capacitor C1 that is higher than the clamp reference voltage V (N3) of the node N3 is not completed, the comparator X1 of the first control circuit 32 sends an H level control signal to the control node N4 during the synchronization period. And the switching element SW1 of the switching circuit 34 is turned on. The comparator X2 of the second control circuit 36 outputs an H level control signal to the control node N7, the switching element SW3 is turned on, the power supply potential Vdd and the capacitor C2 are connected, and the capacitor C2 is charged. When the signal at the control node N5 exceeds the threshold voltage Vt of the switching element SW2 of the switching circuit 34, the switching element SW2 is turned on. In the synchronization period, the switching elements SW1 and SW2 of the switching circuit 34 are turned on, the current (clamp current) I1 supplied from the current source I1 is supplied to the node N2, and the input capacitor C1 is charged.

  In the burst signal period and the video signal period after the end of the synchronization period, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4, and the switching element SW1 of the switching circuit 34 is in the OFF state. become. Also, the comparator X2 of the second control circuit 36 outputs an L level control signal to the control node N7, the switching element SW3 is turned off, and the power supply potential Vdd and the capacitor C2 are disconnected. The electric charge at both ends of the capacitor C2 is discharged, and the switching element SW2 is kept on and supplied from the current source I1 until the voltage V (N5) of the control node N5 becomes lower than the threshold voltage Vt of the switching element SW2. The current (clamp current) I1 is supplied to the node N2, and the input capacitor C1 is charged.

  Thus, in the burst signal period and the video signal period, even after the switching element SW1 of the switching circuit 34 is turned off, the voltage V (N5) of the control node N5 becomes less than the threshold voltage Vt of the switching element SW2. During this period, the switching element SW2 is kept on and the input capacitor C1 is charged by the current I1, so that the charging period of the input capacitor C1 per cycle of the video signal can be extended and the input capacitor C1 is charged. It is possible to reduce the number of video signal cycles required to complete the process.

  Therefore, in the present embodiment, the charging time required for charging the input capacitor C1 can be shortened without reducing the capacitance of the input capacitor C1 and without increasing the clamp current I1 required for charging.

  Further, the extension width (extension period) of the charging period in one cycle can be arbitrarily changed by setting the capacitance value of the capacitor C2 and the resistance value of the resistor R1, and other control signals (for example, external to the clamp circuit 30). No control signal or the like input from is required.

  In the clamp circuit 30 of the present embodiment, the voltage V (N2) at the node N2 in the synchronization period is higher than the reference voltage V (N6) at the node N6 and higher than the clamp reference voltage V (N3) at the node N3. The charging of the input capacitor C1 is completed, which is low and the voltage V (N2) of the node N2 in the burst signal period and video signal period after the end of the synchronization period is higher than the clamp reference voltage V (N3) of the node N3. In this case, during the synchronization period, the comparator X1 of the first control circuit 32 outputs an H level control signal to the control node N4, and the switching element SW1 of the switching circuit 34 is turned on. Further, the comparator X2 of the second control circuit 36 outputs an L level control signal to the control node N7, the switching element SW3 maintains the OFF state, and the control signal output to the control node N5 is also at the L level. Therefore, the switching element SW2 is kept off. In the synchronization period, the switching element SW1 of the switching circuit 34 is turned on, the current (clamp current) I1 supplied from the current source I1 is supplied to the node N2, and the input capacitor C1 is charged.

  In the burst signal period and the video signal period after the end of the synchronization period, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4, and the switching element SW1 of the switching circuit 34 is in the OFF state. become. On the other hand, in the second control circuit 36, since the control signals output to the control node N7 and the control node N5 are both at the L level, the switching element SW2 maintains the off state.

  As described above, when the charging of the input capacitor C1 is completed, the second control circuit 36 does not charge the capacitor C2 in the second control circuit 36 because the switching element SW3 is kept off in the synchronization period. Therefore, when the synchronization period ends, both the switching element SW1 and the switching element SW2 are turned off, and the input capacitor C1 is not charged. That is, in the present embodiment, the reference voltage V (N6) is smaller than the clamp reference voltage V (N3), specifically, the lowest voltage in the synchronization period of the voltage V (N2) of the node N2 after clamping. Since it is set to less than (see FIG. 7), in the second control circuit 36, the control signal of the control node N5 is always at L level, and the switching element SW2 is kept in the OFF state.

  Therefore, since the input capacitor C1 is charged only during the synchronization period, overcharging of the input capacitor C1 can be prevented.

  In the present embodiment, as a specific example, the second control circuit 36 is configured by the resistor R1, the capacitor C2, and the switching element SW3. However, the present invention is not limited to this, and an arbitrary fixed period such as a circuit using a counter, Any circuit that can hold the control level of the switching element SW2 may be used, and the configuration thereof is not particularly limited.

  [Second Embodiment]

  Hereinafter, a signal processing system (semiconductor device, clamp circuit) and a clamp operation according to a second embodiment of the present invention will be described in detail with reference to the drawings. Note that the signal processing system (semiconductor circuit, clamp circuit) and the clamping operation of the present embodiment include substantially the same configuration and operation as the first embodiment, and therefore substantially the same configuration as the first embodiment. The parts that are operations are indicated by the same reference numerals, and detailed description thereof is omitted.

  First, the configuration of the signal processing system according to the present embodiment will be described. An example of a schematic configuration of the signal processing system of this embodiment is shown in FIG. The signal processing system 40 of the present embodiment shown in FIG. 8 is the same as the signal processing system of the first embodiment in the configuration and operation of the second control circuit 46 of the clamp circuit 44 of the semiconductor device 42 in the signal processing system 40. 10 differs from the second control circuit 36 of the clamp circuit 30 of the semiconductor device 20 in FIG. In addition, the semiconductor device 42 of this embodiment includes a control signal source 43 that outputs a control signal to the second control circuit 46.

  FIG. 9 shows a circuit diagram of a specific example of the clamp circuit 44 of the present embodiment. As described above, the clamp circuit 44 according to the present embodiment is different in configuration and operation of the second control circuit 46 from the second control circuit 36 of the clamp circuit 30 according to the first embodiment. The configuration of will be described.

  The second control circuit 46 of the present embodiment compares the reference voltage V (N6) of the node N6 with the signal voltage of the node N9, and when the reference voltage V (N6) is higher, the second control circuit 46 is at the H level. Is output to the control node N11, a switching element SW4 connecting the node N9 and the node N2, and a capacitor C3 provided between the node N9 and the ground potential Vss. . Note that on / off of the switching element SW4 is controlled (turned on at H level) by a control signal of the control node N10.

  Next, the clamp operation by the clamp circuit 44 of this embodiment and the voltage of each node (including the control node) will be described.

  First, the clamp operation and each node voltage when the input capacitor C1 is not fully charged will be described. FIG. 10 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 44 when the charging of the input capacitor C1 is not completed. FIG. 11 shows an example of each node voltage of the clamp circuit 44.

  As shown in FIG. 11, when the charging of the input capacitor C1 is not completed, the voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6 and after the synchronization period ends. The voltage V (N2) at the node N2 during the burst signal period and the video signal period is higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 44 is substantially the same as the operation when the charging of the input capacitor C1 is not completed in the first embodiment. During the synchronization period, the comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 10: step 300), and the clamp reference voltage V (N3) is at the node N2. Since it is equal to or higher than the voltage V (N2) (FIG. 10: Step 302), the comparator X1 outputs an H level control signal to the control node N4, and the switching element SW1 is turned on (FIG. 10: Step 304, FIG. 11). : Timing t2a).

  On the other hand, the operation of the second control circuit 46 of the clamp circuit 44 will be described. Before the start of the synchronization period, an H level control signal is input to the second control circuit 46 from the outside of the clamp circuit 44 to the control node N10 (FIG. 10: step 400), and the switching element SW4 is turned on ( FIG. 10: Step 402, FIG. 11: Timing t1a).

  When the switching element SW4 is turned on, the voltage V (N2) of the node N2 is sampled to the voltage V (N9) of the node N9 (V (N2) = V (N9), FIG. 10: Step 404), and the capacitance C3 is charged (FIG. 10: Step 406). The comparator X3 compares the reference voltage V (N6) at the node N6 with the voltage V (N9) at the node N9 (FIG. 10: step 408). When the reference voltage V (N6) is less than the voltage V (N9) of the node N9 (FIG. 10: negative in step 410), an L level control signal is output to the control node N11, and the switching element SW2 is kept off. (FIG. 10: Step 412, FIG. 11: Timing t1a to t2a).

  In the second control circuit 46, the reference voltage V (N6) is equal to or higher than the voltage V (N2) at the node N2 and equal to or higher than the voltage V (N9) at the node N9 during the synchronization period (FIG. 4: in step 410). (Yes) The comparator X3 outputs an H level control signal to the control node N11, and the switching element SW2 is turned on (FIG. 4: step 414, FIG. 11: timing t2a).

  Thus, the switching element SW1 controlled by the first control circuit 32 is turned on at the timing t1a, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. At the timing t2a, the switching element SW2 controlled by the second control circuit 46 is also turned on, and the input capacitor C1 is charged by the current I1 supplied from the current source I1.

  During the synchronization period of the video signal, the voltage V (N2) of the node N2 <the reference voltage V (N6) <the clamp reference voltage V (N3) in the first control circuit 32 (FIG. 10: affirmative in step 306) In the period from the timing t2a to t4a in FIG. 11, the voltage V (N4) of the control node N4 becomes H level, the switching element SW1 of the switching circuit 34 is turned on, and the input capacitance is determined by the current I1 supplied from the current source I1. C1 is charged.

  On the other hand, in the second control circuit 36, an L level control signal is input from the outside of the clamp circuit 44 to the control node N10 during the synchronization period (FIG. 10: step 416), and the switching element SW4 is turned off (FIG. 10). 10: Step 418, FIG. 11: Timing t3a).

  When the switching element SW4 is turned off, the voltage V (N9) (V (N2) = V (N9)) of the node N9 sampled at the node N2 is held by the capacitor C3. At this time, since the voltage V (N2) of the node N2 = the voltage V (N9) of the node N9 <the reference voltage V (N6), the control signal of the control node N11 holds the H level. The on state is maintained. (FIG. 10: Step 420, FIG. 11: Timing t3a to t5a).

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 11: timing t4a), the reference voltage V (N6) <the clamp reference voltage V (N3) <the voltage V (N2) of the node N2 Therefore, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 10: step 308, FIG. 11: timing t4a).

  On the other hand, in the second control circuit 46, since the switching element SW4 is in the OFF state as described above, the comparator X3 has the voltage V (N2) of the node N2 = the voltage V (N9) of the node N9 due to the capacitor C3. Is held, the control signal of the control node N11 is held at the H level, and the ON state of the switching element SW2 is held. (FIG. 10: Step 420, FIG. 11: Timing t3a to t5a).

  Thereafter, in the second control circuit 46, during the burst signal period and the video signal period, an H level control signal is input from the outside of the clamp circuit 44 to the control node N10 (FIG. 10: step 422), and the switching element SW4 is turned on. A state is reached (FIG. 10: Step 424, FIG. 11: Timing t5a).

  When the switching element SW4 is turned on, the voltage V (N2) of the node N2 is sampled to the voltage V (N9) of the node N9 (V (N2) = V (N9), FIG. 10: step 426). At this time, since the reference voltage V (N6) <the voltage V (N2) of the node N2 = the voltage V (N9) of the node N9 (FIG. 10: step 428), the comparator X3 has the reference voltage V ( N6) and the voltage V (N9) of the node N9 are compared (FIG. 10: Step 430). As a result, the control signal of the control node N11 becomes L level, and the switching element SW2 is turned off. (FIG. 10: Step 432, FIG. 11: Timing t5a).

  Since the switching element SW1 is already in the off state and the switching element SW2 is also in the off state, no current is supplied from the current source I1 to the node N2, so that the charging of the input capacitor C1 is stopped.

  Next, a clamp operation and each node voltage when the input capacitor C1 has been charged will be described. FIG. 12 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 44 when the charging of the input capacitor C1 is completed. FIG. 13 shows an example of each node voltage of the clamp circuit 44.

  As shown in FIG. 13, when the charging of the input capacitor C1 is completed, the voltage V (N2) of the node N2 in the synchronization period is higher than the reference voltage V (N6) of the node N6, and the clamp of the node N3 The voltage V (N2) at the node N2 in the burst signal period and the video signal period after the end of the synchronization period is lower than the reference voltage V (N3) and higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 44 is substantially the same as the operation when the charging of the input capacitor C1 in the first embodiment is completed. During the synchronization period, the comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 12: step 350), and the clamp reference voltage V (N3) is at the node N2. Since it is equal to or higher than the voltage V (N2) (FIG. 12: step 352), an H level control signal is output from the comparator X1 to the control node N4, and the switching element SW1 is turned on (FIG. 12: step 354, FIG. 13). : Timing t1b).

  On the other hand, the operation of the second control circuit 46 of the clamp circuit 44 will be described. During the synchronization period, an L level control signal is input to the second control circuit 46 from the outside of the clamp circuit 44 to the control node N10 (FIG. 12: step 450), and the switching element SW4 is turned off (FIG. 12: Step 452, FIG. 13: timing t2b).

  When the switching element SW4 is turned off, the voltage V (N2) of the node N2 that has been sampled to the voltage V (N9) of the node N9 is held (V (N2) = V (N9)). (FIG. 12: Step 454). At this time, since the reference voltage V (N6) <the voltage V (N2) of the node N2 = the voltage V (N9) of the node N9 (FIG. 12: step 456), the comparator X3 has the reference voltage V ( N6) and the voltage V (N9) of the node N9 are compared (FIG. 12: step 458), the control signal of the control node N11 becomes L level, and therefore the switching element SW2 maintains the OFF state. (FIG. 12: Step 460, FIG. 13: Timing t2b).

  Thus, during the synchronization period of the video signal, the switching element SW1 controlled by the first control circuit 32 is turned on at timing t1b, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. . On the other hand, the switching element SW2 controlled by the second control circuit 46 maintains the off state. However, since the switching element SW1 is in the on state, the input capacitor C1 is charged by the current I1 supplied from the current source I1. The

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 13: timing t3b), reference voltage V (N6) <clamp reference voltage V (N3) <voltage V (N2) of node N2 Therefore, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 12: step 358, FIG. 13: timing t3b).

  On the other hand, in the second control circuit 46, as described above, the comparator X3 has the voltage V (N2) of the node N2 = the voltage V (N9 of the node N9) until the switching element SW4 is turned on from the off state. ) Is held, the control signal of the control node N11 is held at L level, and the OFF state of the switching element SW2 is held. (FIG. 13: Timing t2b-t4b).

  In the second control circuit 46, an H level control signal is input from the outside of the clamp circuit 44 to the control node N10 during the burst signal period and the video signal period (FIG. 12: step 462), and the switching element SW4 is turned on. (FIG. 12: Step 464, FIG. 13: Timing t4b).

  When the switching element SW4 is turned on, the voltage V (N2) at the node N2 is sampled to the voltage V (N9) at the node N9 (V (N2) = V (N9), FIG. 12: step 466). At this time, since the reference voltage V (N6) <the voltage V (N2) of the node N2 = the voltage V (N9) of the node N9 (FIG. 12: step 468), the comparator X3 has the reference voltage V ( N6) and the voltage V (N9) of the node N9 are compared (FIG. 12: step 470), the control signal of the control node N11 becomes L level, and therefore the switching element SW2 maintains the OFF state. (FIG. 12: Step 472, FIG. 13: Timing t4b).

  Since the switching element SW1 is already in the off state and the switching element SW2 is also in the off state, no current is supplied from the current source I1 to the node N2, so that the charging of the input capacitor C1 is stopped.

  Thus, during the burst signal period and the video signal period, since both the switching element SW1 and the switching element SW2 of the switching circuit 34 are in the off state, the current I1 is not supplied from the current source I1, and the input capacitor C1 is not charged.

  As described above, the clamp circuit 44 in the semiconductor device 42 of the signal processing system 40 according to the present embodiment includes the first control circuit 32, the switching circuit 34, and the second control circuit 46. The switching circuit 34 includes a switching element SW1 and a switching element SW2 that are connected in parallel and turned on by an H level control signal between the current source I1 and the node N2 (input capacitance C1). The first control circuit 32 includes a comparator X1, compares the voltage V (N2) of the node N2 with the clamp reference voltage V (N3) of the node N3, and voltage V (N2) ≦ clamp reference voltage V In the case of (N3), an H level control signal is output to the control node N4. The second control circuit 46 is connected to the comparator X3 that compares the reference voltage V (N6) of the node N6 with the voltage V (N9) of the node N9 and outputs a control signal to the control node N11, and the node N9. And a switching element SW4 that connects the node N9 and the node N2. The switching element SW4 is controlled to be turned on when the control signal is at the H level by a control signal input to the control node N10 from the outside of the clamp circuit 44. The comparator X3 compares the voltage V (N9) at the node N9 with the reference voltage V (N6) at the node N6, and if the voltage V (N9) ≦ the reference voltage V (N6), the comparator X3 supplies the control node N11 with H. A level control signal is output.

  The voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6, and the voltage V (N2) of the node N2 in the burst signal period and the video signal period after the synchronization period ends When charging of the input capacitor C1 that is higher than the clamp reference voltage V (N3) of the node N3 is not completed, the comparator X1 of the first control circuit 32 sends an H level control signal to the control node N4 during the synchronization period. And the switching element SW1 of the switching circuit 34 is turned on.

  Further, in the second control circuit 46, an H level control signal is input to the control node N10 from the outside of the clamp circuit 44, the switching element SW4 is turned on, and the voltage V (N9) of the node N9 = the voltage of the node N2 V (N2). Since the voltage V (N9) at the node N9 = the voltage V (N2) at the node N2 <the reference voltage V (N6) at the node N6, the comparator X3 outputs an H level control signal to the control node N11 for switching. The element SW2 is turned on. In the synchronization period, the switching elements SW1 and SW2 of the switching circuit 34 are turned on, the current (clamp current) I1 supplied from the current source I1 is supplied to the node N2, and the input capacitor C1 is charged.

  Further, during the synchronization period, in the second control circuit 46, an L level control signal is input to the control node N10 from the outside of the clamp circuit 44, the switching element SW4 is turned off, and the voltage V of the node N9 is caused by the capacitor C3. (N9) = the voltage V (N2) of the node N2 is held. At this time, since the voltage V (N9) of the node N9 = the voltage V (N2) of the node N2 <the reference voltage V (N6) of the node N6, the control node N11 holds the control signal at the H level, and the switching element SW2 Keep the on state.

  Further, in the burst signal period and the video signal period after the end of the synchronization period, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4, and the switching element SW1 of the switching circuit 34 is in the OFF state. become. In the second control circuit 46, the switching element SW4 is kept off by the L level control signal input to the control node N10, and the voltage V (N9) of the node N9 = the voltage of the node N2 by the capacitor C3. Since V (N2) <the reference voltage V (N6) of the node N6 is held, the control node N11 holds the control signal at the H level, holds the ON state of the switching element SW2, and is supplied from the current source I1. A current (clamp current) I1 is supplied to the node N2, and the input capacitor C1 is charged.

  Thus, in the burst signal period and the video signal period, even after the switching element SW1 of the switching circuit 34 is turned off, the switching element SW2 is kept on and the input capacitor C1 is charged by the current I1. Since the charging period of the input capacitor C1 per cycle of the video signal can be extended, the number of cycles of the video signal required until the charging of the input capacitor C1 is completed can be reduced.

  Therefore, as in the first embodiment, the charging time required for charging the input capacitor C1 can be shortened without reducing the capacitance of the input capacitor C1 and without increasing the clamp current I1 required for charging. it can.

  Further, since the charging period of the switching element SW2 is continued until an H level control signal is input to the control node N10 during the burst signal period and the video signal period, the charging period extension width (extension) is further increased. Period) can be lengthened.

  In the present embodiment, since the adjustment of the charging period of the input capacitor C1 can be controlled by a control signal input to the control node N10, for example, compared with the clamp circuit 30 of the first embodiment, Without increasing the layout of the clamp circuit 44, the charging period in one cycle can be lengthened, and the charging time required for charging the input capacitor C1 can be shortened.

  In addition, when the charging of the input capacitor C1 is completed, the second control circuit 46 controls the on / off of the switching element SW4 based on the control signal input to the control node N10 during the synchronization period. Since the reference voltage V (N6) of N6 <the voltage V (N9) of the node N9 = the voltage V (N2) of the node N2, the control node N11 holds the control signal of L level and the switching element SW2 is turned off. In order to maintain the state, the capacitor C2 is not charged. When the synchronization period ends, the switching element SW1 is turned off and the switching element SW2 is kept off, so that the input capacitor C1 is not charged. That is, in this embodiment, as in the first embodiment, the reference voltage V (N6) is smaller than the clamp reference voltage V (N3). Specifically, the voltage of the node N2 after clamping is In the second control circuit 46, the control signal of the control node N11 is always at L level and the switching element SW2 is kept off because the voltage is set to be lower than the minimum voltage (see FIG. 11) of the synchronization period of V (N2). To do.

  Therefore, since the input capacitor C1 is charged only during the synchronization period, overcharging of the input capacitor C1 can be prevented.

  In the present embodiment, as a specific example, the second control circuit 46 is configured by an S / H circuit (sample hold circuit) using the capacitor C3 and the switching element SW4. Any circuit that can hold the voltage V (N2) may be used, and the configuration thereof is not particularly limited.

  [Third Embodiment]

  Hereinafter, a signal processing system (semiconductor device, clamp circuit) and a clamp operation according to a third embodiment of the present invention will be described in detail with reference to the drawings. Note that the signal processing system (semiconductor circuit, clamp circuit) and the clamp operation of the present embodiment include substantially the same configuration and operation as the first embodiment and the second embodiment. Portions having substantially the same configuration and operation as those of the second embodiment and the second embodiment are indicated by the same reference numerals, and detailed description thereof is omitted.

  First, the configuration of the signal processing system according to the present embodiment will be described. An example of a schematic configuration of the signal processing system according to the present embodiment is shown in FIG. In the signal processing system 50 of the present embodiment shown in FIG. 14, the configuration and operation of the second control circuit 56 of the clamp circuit 54 of the semiconductor device 52 in the signal processing system 50 are the same as those in the first embodiment and the second embodiment. This is different from the embodiment. In addition, the semiconductor device 52 of the present embodiment includes a control signal source 53 that outputs a control signal to the second control circuit 56.

  FIG. 15 shows a circuit diagram of a specific example of the clamp circuit 54 of the present embodiment. As described above, the clamp circuit 54 of the present embodiment differs from the first embodiment and the second embodiment in the configuration and operation of the second control circuit 56. explain.

  The second control circuit 56 of the present embodiment compares the reference voltage V (N6) of the node N6 with the voltage V (N2) of the node N2, and when the reference voltage V (N6) is higher, The comparator X4 that outputs the control signal to the control node N12 and a DFF (D flip-flop) are provided. The DFF uses the signal output to the control node N12 as a data input, the control node N13 as a control signal input, and the control node N14 of the switching element SW2 as an output. That is, the DFF has a function of outputting and holding the signal state of the control node N12 at the rising timing of the control signal (pulse) of the control node N13 to the control node N14.

  Next, the clamp operation by the clamp circuit 54 of this embodiment and the voltage of each node (including the control node) will be described.

  First, the clamp operation and each node voltage when the input capacitor C1 is not fully charged will be described. FIG. 16 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 54 when the charging of the input capacitor C1 is not completed. FIG. 17 shows an example of each node voltage of the clamp circuit 54.

  As shown in FIG. 17, when the charging of the input capacitor C1 is not completed, the voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6 and after the synchronization period ends. The voltage V (N2) at the node N2 during the burst signal period and the video signal period is higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 44 is substantially the same as the operation in the case where the charging of the input capacitor C1 is not completed in the first and second embodiments. During the synchronization period, the comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 16: step 500), and the clamp reference voltage V (N3) is at the node N2. Since it is equal to or higher than the voltage V (N2) (FIG. 16: Step 502), the comparator X1 outputs an H level control signal to the control node N4, and the switching element SW1 is turned on (FIG. 16: Step 504, FIG. 17). : Timing t1a).

  On the other hand, the operation of the second control circuit 56 of the clamp circuit 54 will be described. The comparator X4 compares the reference voltage V (N6) at the node N6 with the voltage V (N2) at the node N2 (FIG. 16: step 600). During the synchronization period, since the reference voltage V (N6) is equal to or higher than the voltage V (N2) of the node N2 (FIG. 16: step 602), an H level control signal is output from the comparator X4 to the control node N12 (FIG. 16). : Step 604, FIG. 17: Timing t1a).

  If a control signal (pulse) is input from the outside of the clamp circuit 54 to the control node N13 during the synchronization period (FIG. 16: step 606, FIG. 17: timing t2a), the DFF will control the H of the control node N12 at this time. The voltage level, which is a level, is output to the control node N14 (FIG. 16: step 608, timing t2a in FIG. 17).

  Since the control node N14 is at the H level, the switching element SW2 is turned on (FIG. 16: Step 610, FIG. 17 timing t2a).

  Thus, the switching element SW1 controlled by the first control circuit 32 is turned on at the timing t1a, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. At the timing t2a, the switching element SW2 controlled by the second control circuit 56 is also turned on, and the input capacitor C1 is charged by the current I1 supplied from the current source I1.

  During the video signal synchronization period, the voltage V (N2) of the node N2 <the reference voltage V (N6) <the clamp reference voltage V (N3) in the first control circuit 32 (FIG. 16: affirmative in step 506) In the period from timing t1a to t3a in FIG. 17, the voltage V (N4) of the control node N4 becomes H level, the switching element SW1 of the switching circuit 34 is turned on, and the input capacitance is determined by the current I1 supplied from the current source I1. C1 is charged.

  On the other hand, in the second control circuit 56, since the control signal (pulse) is not input to the control node N13, in the DFF, the control signal of the control node N14 holds the H level, and thus the switching element SW2 keeps the on state. To do.

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 17: timing t3a), the reference voltage V (N6) <the clamp reference voltage V (N3) <the voltage V (N2) of the node N2 Therefore, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 16: step 508, FIG. 17: timing t3a).

  On the other hand, in the second control circuit 56, the control signal (pulse) is not input to the control node N13 during the burst signal period and the video signal period. Therefore, in the DFF, the control signal of the control node N14 holds the H level. The switching element SW2 is kept on.

  Therefore, in the burst signal period and the video signal period, the switching element SW1 is in the off state, but the switching element SW2 is in the on state. Therefore, a current is supplied from the current source I1 to the node N2, and accordingly, the input capacitance C1. Is charged.

  Next, a clamp operation and each node voltage when the input capacitor C1 has been charged will be described. FIG. 18 shows a flowchart of an example of the flow of the clamping operation in the clamping circuit 54 when the charging of the input capacitor C1 is completed. FIG. 19 shows an example of each node voltage of the clamp circuit 54.

  As shown in FIG. 19, when the charging of the input capacitor C1 is completed, the voltage V (N2) of the node N2 in the synchronization period is higher than the reference voltage V (N6) of the node N6, and the clamp of the node N3 The voltage V (N2) at the node N2 in the burst signal period and the video signal period after the end of the synchronization period is lower than the reference voltage V (N3) and higher than the clamp reference voltage V (N3) at the node N3.

  The operation of the first control circuit 32 of the clamp circuit 54 is substantially the same as the operation in the case where the charging of the input capacitor C1 is completed in the first and second embodiments. During the synchronization period, the comparator X1 compares the clamp reference voltage V (N3) at the node N3 with the voltage V (N2) at the node N2 (FIG. 18: step 550), and the clamp reference voltage V (N3) is at the node N2. Since it is equal to or higher than the voltage V (N2) (FIG. 18: step 552), an H level control signal is output from the comparator X1 to the control node N4, and the switching element SW1 is turned on (FIG. 18: step 554, FIG. 19). : Timing t1b).

  On the other hand, the operation of the second control circuit 56 of the clamp circuit 54 will be described. In the second control circuit 56, the comparator X4 compares the reference voltage V (N6) at the node N6 with the voltage V (N2) at the node N2 (FIG. 18: step 650). During the synchronization period, the reference voltage V (N6) <the voltage V (N2) of the node N2 (FIG. 18: step 652). An L level control signal is output from the comparator X4 to the control node N12 (FIG. 16: Step 654, FIG. 19: timing t1b).

  When a control signal (pulse) is input from the outside of the clamp circuit 54 to the control node N13 during the synchronization period (FIG. 18: step 656, FIG. 19: timing t2b), the DFF is the L of the control node N12 at this time. The voltage level, which is a level, is output to the control node N14 (FIG. 18: step 658, timing t2b in FIG. 19).

  Since the control node N14 is at the L level, the switching element SW2 is turned off (FIG. 18: step 660, timing t2b in FIG. 19).

  Thus, during the synchronization period of the video signal, the switching element SW1 controlled by the first control circuit 32 is turned on at timing t1b, and the input capacitor C1 is charged by the current I1 supplied from the current source I1. . On the other hand, although the switching element SW2 controlled by the second control circuit 56 maintains the off state, the input capacitor C1 is charged by the current I1 supplied from the current source I1 when the switching element SW1 is in the on state. The

  During the synchronization period of the video signal, in the first control circuit 32, reference voltage V (N6) <voltage V (N2) of node N2 <clamp reference voltage V (N3) (FIG. 18: affirmative in step 556) During the period from timing t1b to t3b in FIG. 19, the voltage V (N4) of the control node N4 becomes H level, the switching element SW1 of the switching circuit 34 is turned on, and the input capacitance is increased by the current I1 supplied from the current source I1. C1 is charged.

  On the other hand, in the second control circuit 56, since the control signal (pulse) is not input to the control node N13, in the DFF, the control signal of the control node N14 maintains the L level, and therefore the switching element SW2 maintains the off state. To do.

  When the synchronization period of the video signal ends and the burst signal period and the video signal period (FIG. 13: timing t3b), reference voltage V (N6) <clamp reference voltage V (N3) <voltage V (N2) of node N2 Therefore, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4. As a result, the switching element SW1 of the switching circuit 34 is turned off (FIG. 18: step 558, FIG. 19: timing t3b).

  On the other hand, in the second control circuit 56, the control signal (pulse) is not input to the control node N13 during the burst signal period and the video signal period. Therefore, in the DFF, the control signal of the control node N14 maintains the L level. The switching element SW2 is kept off.

  Thus, during the burst signal period and the video signal period, since both the switching element SW1 and the switching element SW2 of the switching circuit 34 are in the off state, the current I1 is not supplied from the current source I1, and the input capacitor C1 is not charged.

  As described above, the clamp circuit 54 in the semiconductor device 52 of the signal processing system 50 according to the present embodiment includes the first control circuit 32, the switching circuit 34, and the second control circuit 56. The switching circuit 34 includes a switching element SW1 and a switching element SW2 that are connected in parallel and turned on by an H level control signal between the current source I1 and the node N2 (input capacitance C1). The first control circuit 32 includes a comparator X1, compares the voltage V (N2) of the node N2 with the clamp reference voltage V (N3) of the node N3, and voltage V (N2) ≦ clamp reference voltage V In the case of (N3), an H level control signal is output to the control node N4. The second control circuit 56 outputs a comparison result obtained by comparing the reference voltage V (N6) of the node N6 with the voltage V (N9) of the node N9 to the control node N12, and outputs the comparison result to the control node N12. And a DFF having the control node N13 as a control signal input and the control node N14 of the switching element SW2 as an output. The comparator X3 compares the voltage V (N2) at the node N2 with the reference voltage V (N6) at the node N6, and if the voltage V (N2) ≦ the reference voltage V (N6), the comparator X3 supplies the control node N12 with H. A level signal is output. The DFF outputs the signal state of the control node N12 at the rising timing of the control signal (pulse) input to the control node N13 from the outside of the clamp circuit 54 to the control node N14 and holds it.

  The voltage V (N2) of the node N2 in the synchronization period is lower than the reference voltage V (N6) of the node N6, and the voltage V (N2) of the node N2 in the burst signal period and the video signal period after the synchronization period ends When charging of the input capacitor C1 that is higher than the clamp reference voltage V (N3) of the node N3 is not completed, the comparator X1 of the first control circuit 32 sends an H level control signal to the control node N4 during the synchronization period. And the switching element SW1 of the switching circuit 34 is turned on.

  In the second control circuit 56, when a control signal (pulse) is input to the control node N13 from the outside of the clamp circuit 54, the DFF sets the voltage level that is the H level of the control node N12 at this time to the control node N14. And the switching element SW2 is turned on. In the synchronization period, the switching elements SW1 and SW2 of the switching circuit 34 are turned on, the current (clamp current) I1 supplied from the current source I1 is supplied to the node N2, and the input capacitor C1 is charged.

  In the burst signal period and the video signal period after the end of the synchronization period, the comparator X1 of the first control circuit 32 outputs an L level control signal to the control node N4, and the switching element SW1 of the switching circuit 34 is in the OFF state. become. In the second control circuit 46, since no control signal (pulse) is input to the control node N13, in the DFF, the control signal of the control node N14 maintains the L level, and therefore the switching element SW2 maintains the off state. The current (clamp current) I1 supplied from the current source I1 is supplied to the node N2, and the input capacitor C1 is charged.

  Thus, in the burst signal period and the video signal period, even after the switching element SW1 of the switching circuit 34 is turned off, the switching element SW2 is kept on and the input capacitor C1 is charged by the current I1. Since the charging period of the input capacitor C1 per cycle of the video signal can be extended, the number of cycles of the video signal required until the charging of the input capacitor C1 is completed can be reduced.

  Therefore, as in the first and second embodiments, the input capacitor C1 is required to be charged without reducing the capacitance of the input capacitor C1 and without increasing the clamp current I1 required for charging. Charging time can be shortened.

  Further, as shown in FIG. 17, the charging period of the switching element SW2 can be continued until the synchronization period of the next cycle, so that the extension width (extension period) of the charging period in one cycle can be further increased. .

  In the present embodiment, the charging period of the input capacitor C1 can be controlled by a control signal (pulse) input to the control node N13 of the DFF of the second control circuit 56. For example, the second embodiment Unlike the embodiment, the S / H circuit (see FIG. 9, the capacitor C3 and the switching element SW4) for holding the voltage V (N2) of the node N2 is not required, and the area of the clamp circuit 54 (substrate 22) can be further increased. Can be reduced.

  When charging of the input capacitor C1 is completed, the second control circuit 56 in the synchronization period satisfies the reference voltage V (N6) of the node N6 <the voltage V (N2) of the node N2, so that the control node N14 Holds the L level control signal and keeps the switching element SW2 in the OFF state, and therefore does not charge the capacitor C2. When the synchronization period ends, the switching element SW1 is turned off and the switching element SW2 is kept off, so that the input capacitor C1 is not charged. That is, in the present embodiment, as in the first and second embodiments, the reference voltage V (N6) is smaller than the clamp reference voltage V (N3). Specifically, Since the voltage V (N2) of the node N2 after clamping is set to be less than the lowest voltage (see FIG. 17) in the synchronization period, the control signal of the control node N14 is always at the L level in the second control circuit 56, and switching The element SW2 is kept off.

  Therefore, since the input capacitor C1 is charged only during the synchronization period, overcharging of the input capacitor C1 can be prevented.

  In the present embodiment, the second control circuit 46 is configured to include a DFF. However, the present invention is not limited to this, and the voltage of the control node N12 that is an input signal during the synchronization period, such as another flip-flop circuit, is also included. There is no particular limitation as long as V (N12) can be held as the voltage V (N14) of the control node N14 as an output.

  In the first to third embodiments, the case where the clamp reference voltage V (N3) <the reference voltage V (N6) is described. However, the present invention is not limited to this, and the clamp reference voltage V (N3). = Reference voltage V (N6) may be used, but as described in the first to third embodiments, the clamp reference voltage V (N3) <the reference voltage V (N6). This is preferable because overcharging of the input capacitor C1 can be prevented. Further, it is preferable that the difference between the clamp reference voltage V (N3) and the reference voltage V (N6) is small.

  In the first to third embodiments, the case where the switching elements SW (SW1 to SW4) are MOS transistors has been described. However, the present invention is not limited to this, and other commonly used transistors such as bipolar transistors are used. These switching elements may be used. Further, the comparator X (X1 to X4) is not particularly limited, and a generally used circuit (comparison circuit) may be used as the comparator.

  In addition, the configuration and operation of the clamp circuit described in the first to third embodiments are examples, and can be changed according to the situation without departing from the gist of the present invention. Needless to say.

10, 40, 50 Signal processing system 20, 42, 52 Semiconductor device (LSI)
22 Substrate 30, 44, 54 Clamp circuit 32 First control circuit 34 Switching circuit 36, 46, 56 Second control circuit X1, X2, X3, X4 Comparator N0, N1, N2, N3, N6, N9, N12 Node N4 , N5, N7, N10, N11, N13, N14 Control node C1 Input capacitance C2, C3 Capacitance R1 Resistance SW1, SW2, SW3, SW4 Switching element

Claims (10)

A first switching element disposed between a first capacitor to which a signal is input and a current supply source;
A second switching element disposed between the current supply source and the first capacitor;
A first control unit for connecting the first switching element when the signal is in a synchronization period;
A second controller for connecting the second switching element when the signal is in the synchronization period and in a burst period;
Clamp circuit with The first control unit connects the first switching element when the voltage of the signal input through the first capacitor during the synchronization period is less than a first reference voltage,
The second control unit accumulates voltage information according to the signal when the signal is less than a second reference voltage in the synchronization period and the burst period, and the voltage of the signal is Connecting the second switching element for a predetermined period based on the voltage information when the first reference voltage is exceeded.
The clamp circuit according to claim 1.   The clamp circuit according to claim 2, wherein the first reference voltage is larger than the second reference voltage.   The second control unit includes a capacitance accumulation unit that accumulates charges according to the voltage information. When the voltage of the signal becomes equal to or higher than the first reference voltage, the second control unit converts the charge accumulated in the capacitance accumulation unit. The clamp circuit according to claim 2, wherein the second switching element is connected for a predetermined period based on the second switching element.   In the second control unit, the capacitor storage unit is a second capacitor having one end connected to the ground potential and the other end connected to the third switching element, and is connected in parallel to the second capacitor. The resistance element, the third switching element connecting the second capacitor and the power source, the second reference voltage and the signal are compared, and the signal is less than the second reference voltage, The clamp circuit according to claim 4, further comprising a comparison unit that connects the third switching element.   When the signal is less than the second reference voltage, the second control unit is configured to output the signal based on a comparison unit that connects the second switching element and a charge control signal that is input according to a charging period. A fourth switching element that connects the comparison unit and the first capacitor so as to be input to the comparison unit, and the capacitance storage unit has one end grounded and the other end of the fourth switching element. The clamp circuit according to claim 4, wherein the clamp circuit is a second capacitor connected between a switching element and the comparison unit.   The second control unit is configured to output a signal according to a comparison result obtained by comparing the second reference voltage and the signal, and based on an instruction of a charge control signal input according to a charging period, The clamp circuit of Claim 2 or Claim 3 provided with the holding | maintenance part which hold | maintains and outputs the comparison result output from the comparison part. A first terminal electrically connected to a first capacitor to which a signal is input;
A second terminal electrically connected to the current supply source;
A first switching element disposed between the first capacitor and the current supply source;
A second switching element disposed between the current supply source and the first capacitor;
A first control unit for connecting the first switching element when the signal is in a synchronization period;
A second control unit for connecting the second switching element when the signal is in a synchronization period and in a burst period;
A semiconductor device comprising: A first capacitor to which a signal is input;
A first terminal electrically connected to the first capacitor;
A current source;
A second terminal electrically connected to the current supply source;
A first switching element disposed between the first capacitor and the current supply source;
A second switching element disposed between the current supply source and the first capacitor;
A first control unit for connecting the first switching element when the signal is in a synchronization period;
A second control unit for connecting the second switching element when the signal is in a synchronization period and in a burst period;
A signal processing system. A first control step of connecting, by a first control unit, a first switching element disposed between the first capacitor and a current supply source when a signal input to the first capacitor is in a synchronization period; ,
A second control step of connecting a second switching element disposed between the current supply source and the first capacitor by a second control unit when the signal is in a synchronous period and in a burst period; ,
A signal clamping method comprising:

Images