JPS62165482A - Direct current restoration circuit - Google Patents

Abstract

PURPOSE:To maintain highly accurately the black level of a video signal at a reference electric potential by applying a video signal to one end of a capacitor, comparing the potential of the other end of the capacitor with a reference voltage and discharging the electrostatic charge of the capacitor based on the compared output. CONSTITUTION:When a video signal SGI is applied to one end of the capacitor C2, the gate of an FET 20 is raised at a fixed changing ratio by current I1 supplied from a constant current source 18. When the potential of the source S of the FET 20 exceeds the sum of the reference voltage Vr and the half- amplitude level of hysteresis of a comparator 21, the output Vc of the comparator 21 is inverted, and in a back poach period, i.e., in a period that a clamp pulse PCL is 'H', a leading switch SW is closed by a switch pulse PSW and the gate voltage VG is dropped by the current I2 of a constant current source 19. When the output of the comparator 21 is reduced less than the difference between the voltage Vr and the half-amplitude level, the output is turned to the 'L' level and the switch SW is turned off. Thereby, the voltage VG is led. By repeating said operation, the black level in the back poach period is almost equal to the voltage Vr.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a DC regeneration circuit that regenerates a DC level for digitally processing a video signal that has long been used as an AC signal, and particularly relates to a DC level regeneration circuit. This invention relates to a DC regeneration circuit with improved accuracy.

<Prior Art> FIG. 4 shows a basic configuration for converting a video signal captured by a television camera into a digital image signal.

Video signal S of the television camera 10. A voltage is generated at both ends of the resistor R1, and this video signal SGI is converted by the DC reproduction circuit 11 into a video signal SGo in which the black level of the video signal (for simplicity, a black and white video signal will be described) is set to zero volts, for example. This video signal S. 0 is analog/digital converter 1
2, it is converted into a digital image signal. FIG. 5(A) shows the video signal SG in this case, and FIG. 5(B) shows the video signal SGo.

The video signal SGX has a synchronizing signal S and image signals S and c within a horizontal scanning period Tn of 63.5 μs, and the black level LB of the image signal n S is different from the reference level (zero c level in this case). V, at a very high DC level.

As the image signals S and c become higher in potential than the black level LB, they become whiter and reach a maximum of about 0.7 volts.

Moreover, there is a yn between the synchronization signal S and the image signal S.
There is a pack pouch period TB of approximately 3 μs, and the level of the image signals S and c during this period is
It matches the black level LB of .

The DC reproduction circuit 11 receives this video signal S. black level LB
The analog/4G/digital converter 120 performs 5GoK conversion on the video signal shown in FIG. 5(b), which has a reference level.

Video signal S. S for engineering. A conventional DC regeneration circuit for converting the current to zero is shown in FIG.

The DC regeneration circuit shown in FIG. The level -V is connected to the input terminal of the amplifier 13 via the resistor R3.Thus, the DC level v5 is subtracted from the video signal S to obtain the video signal S., I.

FIG. 6(b) shows a DC regeneration circuit that utilizes the charge holding function of a capacitor. A voltage signal SIG is applied to the base of the transistor 4, a voltage element E is applied to the collector through a resistor R4, and a voltage -E is applied to the emitter through a resistor R5. A parallel circuit of a resistor R6 and a diode D is connected in series with the capacitor C1 between the collector and the common potential point COM. The DC level is held by the capacitor C1, and the positive signal is short-circuited by the diode D1, resulting in the video signal S. 2, the peak value automatically becomes zero (pol)K as shown in FIG.

FIG. 8 shows a DC regeneration circuit that regenerates DC using a clamp pulse. In the DC regeneration circuit shown in FIG. 6(b), the reference level is the synchronizing signal S, as shown in FIG. Since it has an offset by the value of
Even with digital conversion, there is a drawback that the black level does not become exactly zero as digital data. The DC regeneration circuit shown in FIG. 8 improves this drawback. Figure 6 (b)
A switch SW is provided in place of the diode D1 shown in FIG.
is the clamp pulse P. Zeon to L and TB for this period
Set the DC level to zero. With this configuration, the black level LB can be made zero from K. Clamp pulse P. L is obtained by applying the video signal SG to the synchronization separation circuit 15 and using the obtained synchronization signal S to trigger the single-n stabilization circuit 16. The synchronization separation circuit 15 receives the video signal S shown in FIG. 9B)K. 1 is input and the video signal S is sent to the same DC reproducing circuit as in FIG. 6(b).

2 (FIG. 9(B)) and is compared with the voltage -Ve by the comparator 17, the synchronizing signals S and n shown in FIG. 9(C) are obtained at its output terminal. The falling edge of the synchronizing signals s and n triggers the monostable circuit 16, and the crank 7' shown in FIG.
iZRusP. Get L. The gate width of the clamp pulse PcL is the video signal S. The width is selected to be the same as the back porch period TB of 1. With this clamp pulse PcL, switch S
By turning on W, the video signal S becomes zero level during the back porch period TB. 3 is obtained (Figure 9 (e)
).

<Problems to be Solved by the Invention> However, the conventional DC regeneration circuits shown in FIGS. 6 and 8 each have the following problems.

The DC reproduction circuit shown in FIG. 6(a) has S when the video signal SGI is AC coupled. Since the brightness of the image changes depending on the brightness of the image, it has the disadvantage that adjustment of the DC level is required.

In addition to the above-mentioned drawbacks, the direct current reproducing circuit shown in FIG. 6(b) has the problem that the head voltage of the diode D1 becomes an error factor, and the polarity of the video signal is reversed as shown in FIG. 7.

In the DC regeneration circuit shown in Fig. 8, when the switch SW is turned on, the potential at the output end is already close to 0h volts, so
When a semiconductor switch is used as the switch SW, the series resistance becomes large and causes an error. Furthermore, the analog/digital converter 12 used for high-speed signals such as video signals has a reference level not of zero volts but of, for example, 4.3 volts. Therefore, since it is necessary to apply this potential to the common potential point COM, a reference potential source with a large output capacity is required. For this reason, there is a problem in that the heat generation is large, the reliability is lowered, and the cost is increased.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a method in which a video signal is applied to one end of a capacitor, a first constant current is applied to the other end to charge the capacitor, The potential at the other end of this capacitor is compared with a reference voltage by a comparator via an impedance conversion circuit, and a second constant current is passed through the output of this comparator during the back porch period of the video signal to discharge the charge in the capacitor. The black level of the video signal is maintained at a reference potential by adjusting the black level of the video signal.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

A video signal S is connected to one end of the capacitor C2. 1 is applied,
The other end of the constant current source 18 to which voltage +E is applied to one end and one end of the switch SW are connected to the other end. switch S
The other end of W is connected to the other end of a constant current source 19 to which voltage -E is applied.

Further, the other end of the capacitor C2 is connected to the gate of a field effect transistor 20 that performs impedance conversion. The drain D of the field effect transistor 20 has a voltage of E
is applied, and its source SK is connected to the voltage - through resistor R7.
E is applied.

The non-inverting input terminal (+) of the comparator 21 is connected to the source SK of the Vi field effect transistor 20, and its inverting input terminal (-
), a reference voltage V is applied. A cutting edge of the comparator 21 is connected to one input end of an AND gate 22, and a clamp pulse PcL is applied to the other input end of the AND gate 22. The switch SW is opened and closed at the output level of the AND gate 22. The DC reproduced video signal 564Vi is extracted from its source as a source follower of the field effect transistor 20.

Next, the operation of the embodiment shown in FIG. 1 constructed as above will be explained using the waveform diagram shown in FIG. 2.

Gate voltage of field effect transistor 20■. If constant ``1'' is the current supplied by the current source 18, then it increases at a constant rate of change as shown by the dotted line A in Figure 2 (b) due to the current. If we show, we get K as follows.

On the other hand, the potential of the source S of the field effect transistor 20 is N
Gate voltage V in case of channel. From 1 to 2 (v)
Although the potential is high, this potential is connected to the reference voltage vr and the comparator 2.
When the sum of the half width ΔvH of the hysteresis of 1 is exceeded, the output v0 of the comparator 21 is reversed and
)) is at the lH'' level period, the output of the AND gate 22, the switch SW is closed by the output of the AND gate 22 (FIG. 2 (e)), and the current ■2 (I2
〉Gate voltage V at 1). lower. When the output V of the comparator 21 is Cf below the difference between the reference voltage V and the half width ΔVu, the output V of the comparator 21 becomes 1L level, and the switch SW is turned off. Therefore, the gate voltage is V due to charging by the electric current if1. rises. By repeating the above operations, the black level LB during the back porch period TB becomes approximately equal to the reference voltage V.

Next, the accuracy in the case of DC regeneration will be explained.

The comparator 21 has a hysteresis characteristic of a half width ΔvH with respect to changes in input. When being charged with a current of 11 (
1) When the current is discharged at a current of 2, the following equation occurs, and the change occurs as shown by the straight line B in Figure 2 (b).

Therefore, the time τ for which the switch SW is on. N(
In FIG. 2 (E)), considering the charge fluctuation of the capacitor C2, 2ΔVHC2 Δ, (','I2>1,) (3).

Next, the time τ until it turns on is as follows. Therefore, the regenerated DC potential is 2Δ with period τ,
It can be seen that only vH changes. For example, Δ−=2m
V, C2=0.11JP, 11=IIJA
, If I2 = 2001JA, the fluctuation range is 4mV =
0.6% (full scale 0.7 Vχτ, = 400
μS (6 horizontal scanning periods), τ. Nyu is 2 μs. This occurs because the input to the comparator 21 changes slowly, and if a high-speed, high-precision comparator is used, both accuracy and period can be improved.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. Third
In FIG. 1A, the constant current sources 18 and 19 in FIG. 1 are replaced by voltages +E and -E and resistors Rs and R9. This configuration can be realized at low cost. Figure 3 (
B) uses the transistor 23 as the switch SW in FIG. Figure 3 (c) shows the gate voltage V
. This figure shows a configuration in which direct switching is performed using an open collector TTL Nantes gate 23 instead of the switch SW when the value of V is about 2 to 4 V.

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, it is possible to realize a DC regeneration circuit that solves all of the following points pointed out as problems in the prior art.

(a) Since the voltage remaining at both ends of the switch only determines the value of the second constant current, it does not affect accuracy and high accuracy can be maintained.

(b) Since the reference voltage V is an input to the comparator 21, it does not become a load and can be set to any value, allowing freedom in selecting an analog/digital converter.

(c) Since the source follower of field effect transistors is used, the video signal is not inverted, and the input stage of the analog/digital converter can be configured with one stage of field effect transistors, resulting in low cost. .

), the black level can be determined by the reference voltage vr, and can be automatically followed without adjustment.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a waveform diagram showing waveforms of each part of FIG. 1, and FIG. 3 is a circuit diagram showing the configuration of another embodiment of the present invention. , FIG. 4 is a configuration diagram showing a general configuration for converting a video signal into a digital image signal,
Figure 5 is a waveform diagram showing the input and output video signals of the DC regeneration circuit in Figure 4, Figure 6 is a circuit diagram showing the configuration of a conventional DC regeneration circuit, and Figure 7 is the DC voltage in Figure 6 (B). FIG. 3 is a waveform diagram showing the waveform of a video signal after reproduction. 10...TV camera, 11...DC regeneration circuit, 1
2... Analog/digital converter, 15... Synchronous separation circuit, 16... Monostable circuit, 18.19... Constant current source, 21... Comparator, "Gl="GO=sG
l '"G2' SG3 # sG4°-2fJl
4° S, c...image signal, s, n...synchronization signal,
TH...Horizontal scanning period, TB...Pack pouch period, v. gate voltage, PcL...clamp pulse.

Claims (1)

[Claims] A video signal is applied to one end of the capacitor, a first constant current is applied to the other end to charge the capacitor, and the potential at the other end is compared with a reference voltage by a comparator via an impedance conversion circuit. The DC reproducing circuit for the video signal is configured to cause a second constant current to flow during a back porch period of the video signal according to the output of the video signal to discharge the charge in the capacitor and maintain the black level of the video signal at a reference potential.