JPS59848Y2 - clamp circuit - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to a clamp circuit.

As shown in FIG. 1, a conventional clamp circuit includes a clamp charge/discharge capacitor C8 connected between a signal input IN and a signal output OUT, a diode D and a clamp voltage 2 between the output terminal OUT and the ground.

This is a clamp circuit using a diode switch.

Such a diode clamp circuit has a limited clamping characteristic and is not suitable for cases where advanced characteristics such as sag compression ratio are required.

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a synchronous detection/feedback type clamp circuit which has good clamping characteristics and whose semiconductor elements are transistors.

That is, in order to achieve the above object, the present invention is constructed using transistors as a synchronization detection transistor, a waveform shaping transistor, and a clamp switch transistor.

The details of the present invention will be explained below using the drawings.

FIG. 2 is a principle diagram of the clamp circuit, and FIG.

FIG. 4 shows the constituent countries of an embodiment of the present invention.

Generally, a video signal passing through the transmission line 9 circuit network in which no direct current component is transmitted generates low frequency distortion and sag because there is no direct current component.

If this sag is left untreated, it will cause overload and will appear as dark or light colors on the screen.

Therefore, it is necessary to remove the sag by applying a DC component to the video signal using a clamp circuit.

In FIG. 2, co is a charge/discharge capacitor for clamping, vo is a clamp voltage, and SW is a switch that is closed only during the horizontal synchronization signal period.

Although not shown, it is assumed that the impedance of the drive circuit to the input terminal IN is sufficiently low, and the load impedance of the output terminal OUT is sufficiently high.

Under the above operating conditions, the horizontal synchronizing signal tip voltage (1) of the video signal applied to the input terminal IN is subject to fluctuations only to the extent that sag occurs.

Since the switch SW is closed during the period of the horizontal synchronization signal, the capacitor C6 is rapidly charged during this period, and the tip of the horizontal synchronization signal at the output terminal OUT is at the clamp voltage V.

be clamped to. When the horizontal synchronization period is out, the switch SW opens, so the charge charged in the capacitor C8 is discharged through the load impedance connected to the output terminal OUT, but the amount of discharge is small because the output side load impedance is high. .

By repeating this operation, the synchronization tip of the video signal becomes the clamp voltage■.

is clamped and a DC component is applied to improve sag.

The present invention is based on the above operating principle and shows an example of an actual configuration from synchronization detection to a clamp switch.

The explanation will be given below according to FIGS. 3 and 4. In FIGS. 3 and 4, TR1 is a synchronization detection transistor, TR2 is a waveform shaping transistor, and JR3 and JR4 are clamp switch transistors.

The above circuit forms a feedback loop via the buffer transistor TR5.

Further, the base potential vS of the transistor TR1 is set such that the transistor TR1 is conductive only during the period of the negative synchronizing signal.

In the configuration shown in FIG. 3, when there is no signal, the transistor TR1 is conductive, the transistor TR2 is non-conductive, and the transistors TR3 and TR4 are conductive. When a video signal is applied to the input terminal IN, each transistor in the synchronizing signal period The operation of transistor TR1 is conductive, transistor TR2 is non-conductive, transistors TR3 and TR4 are conductive, and the clamp switch is closed only during the synchronization signal period, so that the operation principle is satisfied.

In addition, in the structure shown in Fig. 4, if the time constant of the capacitor C1 is set to a sufficiently large value, when there is no signal, the transistor TR1 becomes conductive, the transistor TR2 becomes non-conductive, and the transistors TR3 and TR4 become non-conductive, and the input terminal IN becomes non-conductive. When a video signal is applied, the operation of each transistor during the synchronizing signal period is such that transistor TR1 is conductive, transistor TR2 is non-conductive, and transistors TR3 and TR4 are conductive, which also satisfies the operating principle and can perform clamp operation. .

As described above, according to the present invention, a synchronous detection/feedback type clamp circuit can be constructed using transistors as all semiconductor elements.

As described above, the present invention has the advantage that it is possible to construct a synchronous detection/feedback type clamp circuit with good clamping characteristics, and that it can be easily integrated into an integrated circuit because the semiconductor elements used can be constructed only from transistors.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional clamp circuit, FIG. 2 is a principle diagram of the clamp circuit, and FIGS. 3 and 4 are block diagrams showing embodiments of the clamp circuit of the present invention. IN...Input terminal, UOT...Output terminal, TR1-TR5...Transistor, R1-
R7...Resistance, Co. C1...Capacitor, vo...Clamp voltage, ■S...Base voltage, Vcc...
··power supply.

Claims (2)

[Scope of utility model registration request] (1) In the synchronization detection/feedback type clamp circuit, the synchronization detection transistor TR1 is a transistor, the base of which is connected to a DC potential ■S capable of synchronization detection, and the emitter connected to the synchronization detection input via the resistor R1. The collector is connected to the power supply V through the load resistor R2. Further, the collector of the transistor TR1 is connected to the base of the waveform shaping transistor TR2 in the next stage.
The emitter of transistor TR2 is at clamp potential ■. , and the collector of transistor TR2 is connected to load resistance R
3 to the power supply +Vcc, and the collector of the transistor TR2 is connected to the clamp switch transistor T.
Of R3 and R4, the base of the transistor TR3 is connected to the base of the transistor TR3, and the base of the transistor TR3 is connected to the base of the transistor TR4 via the resistor R4, and the base of the transistor TR4 is connected to the clamp potential ■ via the resistor R5. The collector of the transistor TR3 is connected to the power supply Vcc via the resistor R6, the emitter of the transistor TR3 is connected to the collector of the transistor TR4, the emitter of TR3 is connected to the clamping capacitor C6, and the emitter of the transistor TR4 is connected to the collector of the transistor TR4. is the clamp potential ■. A clamp circuit configured by being connected to. (2) Collector of transistor TR2 and transistor T
2. The clamp circuit according to claim 1, wherein the clamp circuit is constructed by inserting a capacitor C1 between the base of R3.