JPH0666902B2 - Clamp circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clamp circuit used for reproducing a direct current component of a video signal, for example, a switch circuit using a switch capacitor.

[Outline of Invention]

In the clamp circuit for fixing a signal having a direct current level to a predetermined direct current level according to the present invention, charges accumulated in a first capacitor having a small capacity by an input signal in a predetermined period are charged in a remaining period other than the predetermined period. By transferring to a second capacitor having a capacity sufficiently larger than that of the first capacitor, a large time constant can be obtained and the whole circuit can be integrated into a circuit, and at the same time, it is possible to perform accurate clamp operation against noise. is there.

[Conventional technology]

A clamp circuit for fixing an input signal having a certain DC level to a required constant DC level is used, for example, as a DC component reproducing circuit of a video signal. An example of such a clamp circuit is shown in FIG. In this clamp circuit, a clamp operation is performed in response to a clamp pulse supplied to the base of the switching transistor 101 for each horizontal period (1H), and the pedestal level (base) of the input signal V _I that is a video signal is Level) is fixed to the clamp potential Eco provided by the DC power supply 102. That is, in Pedeisutaru period where the input signal V _I is in Pede chair barrel level, the transistor 101 is turned on the output signal Vo is clamp potential Eco
It will be constant. Further, the input signal V supplied via the transistor 104 of the emitter follower is supplied to the capacitor 103.
Charges corresponding to the difference voltage V _do between _I (pedestal level) and the clamp potential Eco are accumulated. On the other hand, during the remaining period other than the pedestal period including the valid period in which the video signal exists, the input signal V _I is applied to the transistor 10 as described above.
It is output as an output signal Vo via 4 and the capacitor 103. At this time, since the charge corresponding to the difference voltage V _do is accumulated in the capacitor 103, the output signal Vo is clamped at the clamp potential Eco. A clamping operation in which such an operation is repeated is achieved.

[Problems to be solved by the invention]

By the way, actually, a video signal usually contains a noise component, and it is extremely rare that the pedestal portion has a high S / N ratio. In-circuit noise may also mix into the pedestal. Therefore, in the above-described conventional clamp circuit, the noise component existing in the pedestal portion is also held in the capacitor 103 every horizontal period (1H), and a horizontal line corresponding to the degree of noise is generated on the screen to improve the image quality. There is a risk that it will be significantly deteriorated. Therefore, normally, by setting a large time constant RC determined by the resistance R between the collector and emitter of the transistor 101 and the capacitance C of the capacitor 103, for example, only a frequency component of 300 Hz or less is tracked. , The noise holding state is made inconspicuous on the screen. In order to increase the time constant RC, it is possible to increase either the resistance component R or the capacitance C, but increasing the resistance component R is not preferable in terms of frequency characteristics, so the capacitance C is increased. . Considering the strength of the clamp, for example, 0.
A capacitor having a capacitance C of about 1 μF is required.

However, it is impossible to form such a large-capacity capacitor in an integrated circuit, and there is a problem in that when the whole clamp circuit is integrated, only the capacitor 103 becomes an external component. .

Therefore, the present invention has been proposed in view of the above-mentioned conventional problems, and an object thereof is to provide a clamp circuit that is resistant to noise and can be integrated into an integrated circuit.

[Means for solving problems]

In order to achieve the above-mentioned object, an input terminal to which a video signal according to the present invention is supplied, an output terminal from which a video signal is output, and a first terminal connected between the input terminal and the output terminal.
Capacitor, a DC power source connected to the output terminal through the first switch means and providing a clamp potential, and a parallel connection to the first capacitor through the second switch means and the first capacitor. A second capacitor having a large capacitance, wherein the first switch means is turned on for a predetermined period of the pedestal period of the video signal to cause the first capacitor to have a difference between the pedestal level of the video signal and the clamp potential. The charge according to the voltage is accumulated, the second switch means is turned on during the effective period of the video signal to connect the first capacitor and the second capacitor in parallel, and the clamp potential is output from the output terminal. It is characterized in that a video signal clamped at is obtained.

Also, an input terminal to which a video signal is supplied, an output terminal from which the video signal is output, a constant current source connected to the input terminal, and one end of which is connected to the input terminal via a first switch means, The other end is a grounded first capacitor, and the one is connected to the first capacitor via a second switch means, and the other end is a grounded second capacitor having a larger capacity than the grounded first capacitor. And a differential amplifier to which the voltage across the second capacitor and the video signal from the input terminal are input, and the first switch means is turned on for a predetermined period of the pedestal period of the video signal. The charge corresponding to the pedestal level of the video signal is stored in the first capacitor, and the second switch means is turned on during the effective period of the video signal to connect the first capacitor and the second capacitor. Connecting the capacitor, it is characterized in that to obtain a video signal which is maintained at an average value of the pedestal level from the output terminal.

Further, an input terminal to which the video signal is supplied, an output terminal to which the video signal is output, an amplifier for amplifying the video signal from the input terminal, and one end of which is connected to a clamp potential grounded via the first switch means. A DC power source to be applied, a comparator for comparing the output from the amplifier with the output from the DC power source, a first capacitor having one end connected to the comparator and the other end grounded, and one end having the first capacitor A second capacitor having a larger capacity than the first capacitor, which is connected to the first capacitor via the second switch means and has the other end grounded, and a voltage from the second capacitor connected to the third switch means. An adder for adding to the amplifier via the amplifier, and the first switch means is closed during a predetermined period of the pedestal period of the video signal to cause the first capacitor to operate the pedestal of the video signal. The charge corresponding to the difference voltage between the level and the clamp potential is accumulated, and the second switch means and the third switch means are closed during the effective period of the video signal to close the first capacitor and the second capacitor. It is characterized in that a video signal clamped to the clamp potential is obtained from the output terminal by connecting to a capacitor.

[Action]

According to the present invention, the switch capacitor is composed of the first and second capacitors and the switch means, and a large time constant can be obtained without using a large capacity capacitor.

〔Example〕

Hereinafter, embodiments of the clamp circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a clamp circuit of the first embodiment. This clamp circuit and each of the clamp circuits of the second and third embodiments which will be described later use a switch capacitor. Therefore, first, the time constant in the switch capacitor will be described with reference to FIG. The switch 1 is switch-controlled by a predetermined clock signal. As shown in the figure, during a period in which the selection terminal 1a of the switch 1 is connected to the selected terminal 1b side, charges corresponding to an input signal of a substantially constant level are accumulated in the capacitor 2, and the selection terminal 1a of the switch 1 is selected. Terminal
When connected to the 1c side, the charge accumulated in the capacitor 2 is transferred to the capacitor 3 via the switch 1, and the charges corresponding to the capacitance are distributed to the capacitors 2 and 3, respectively. By repeating such operations,
The level of the output signal gradually changes following the input signal. The time constant at this time is determined according to the switching cycle of the switch 1 and the capacitance ratio of the capacitors 2 and 3. Assuming that the switching cycle is constant, the time constant becomes larger as the capacitance of the output side capacitor 3 becomes larger than that of the input side capacitor 2. Therefore, even if the capacitors 2 and 3 each have a small capacitance, a large time constant can be obtained by increasing the capacitance ratio. In other words, it is not necessary to use a large capacity capacitor to obtain a large time constant.

Next, the clamp circuit of the first embodiment will be described with reference to FIG. In FIG. 1, the signal input terminal 11 is connected to the gate of a buffer transistor 12, and the source of the transistor 12 is connected to the drain of a constant current source transistor 13. One end of a small-capacity capacitor 14 is connected to the source of the transistor 12, and a capacitor 15 having a sufficiently larger capacity than this capacitor 14 is connected in parallel to the capacitor 14 via a switching transistor 16. Further, the other end of the capacitor 14 is connected to a DC power supply 18 which supplies a clamp potential Ec ₁ via a switching transistor 17 and a signal output terminal 19. The gates of the switching transistors 17 and 16 are respectively supplied with the respective clock signals .phi. Shown in FIG. The cycle of each clock signal φ is one horizontal period (1H) of the input signal V _I (video signal), and the clock signal φ corresponding to the clamp pulse is synchronized with the pedestal portion of the input signal V _I. . The capacitances of the capacitors 14 and 15 are set so that the time constant is, for example, about 1/300 sec.
For example, it may be about 0.05 pF and 1 pF. As a result, the clamp operation that follows only the fluctuation of the input signal V _I below 300 Hz can be performed.

During the period T ₁ in which the clock signal φ is at the high level, the transistor 17 is turned on and the output signal V ₀ is fixed to the clamp potential Ec ₁ . Further, the capacitor 14 accumulates charges according to the difference voltage Vd ₁ between the input signal V _I and the clamp potential Ec ₁ at the pedestal level supplied via the transistor 12. On the other hand, in the remaining period other than the period T ₁ , that is, the period T ₂ in which the clock signal is at the high level, the transistor 16 is turned on and the input signal V
_I is output as the output signal V ₀ through the parallel circuit of the transistor 12 and the capacitors 14 and 15. At this time, the capacitor 14 and the capacitor 15 are electrically connected by the transistor 16, and the charges corresponding to the capacitance are distributed to the capacitors 14 and 15, respectively. Here, as described above, the input signal V _{I (video} signal) because it contains the normal noise components, the difference between the voltage Vd ₁ accumulated in the capacitor 14 in the period T ₁ in every 1 horizontal period (1H) The values will be slightly different. Therefore, the voltage across the capacitor 15 is the average value of the difference voltage Vd ₁ . Therefore, during this period T ₂ , the video signal portion of the input signal V _I is level-shifted by the average value of the difference voltage Vd ₁ , and the output signal V ₀ without waveform distortion can be obtained. Further, even if a noise component exists in the pedestal portion of the input signal V _I , the noise component does not affect the video signal portion of the output signal V ₀ , and an accurate clamp operation is performed. This is because even if the noise component is held by the capacitor 14,
This is because the voltage between both ends of 15 does not change greatly and is continuously maintained at the average value of the difference voltage Vd ₁ . In addition,
In this embodiment, the voltage across the capacitor 15 changes in response to a gradual level change of the input signal V _I of 300 Hz or less.

Next, the clamp circuit of the second embodiment will be described with reference to FIG. In FIG. 4, signal input terminal
Reference numeral 21 is connected to the gate of a buffer transistor 22, and the source of the transistor 22 is connected to a constant current source 23. In addition, the source of the transistor 22 is a small capacity capacitor via the switching transistor 24.
Connected to 25. The capacitor 25 is connected through a switching transistor 26 to a capacitor 27 having a sufficiently larger capacity than the capacitor 25. This capacitor 27 is connected to the inverting input terminal of the differential amplifier 28,
The non-inverting input terminal of the differential amplifier 28 is the transistor 22
Connected to the source. The output terminal of the differential amplifier 28 is connected to the signal output terminal 29. Each gate of the switching transistors 24 and 26 has a first
Similar to the embodiment of FIG. 3, each clock signal φ, as shown in FIG. 3, is supplied.

During the period T ₁ in which the clock signal φ is at the high level, the transistor 24 is in the ON state, and the capacitor 25 accumulates the charge corresponding to the input signal V _I at the pedestal level. On the other hand, the period T ₂ when the clock signal is high level
In, the transistor 26 is turned on, the capacitor 25 and the capacitor 27 are electrically connected by the transistor 26, and the charges corresponding to the capacitances are distributed to the capacitors 25 and 27, respectively. The voltage across the capacitor 27 is an average value of the pedestal level of the input signal V _I , and a gradual change of 300 Hz or less is detected. The output signal V ₀ according to the difference voltage between the voltage across the capacitor 27 and the input signal V _I is output to the differential amplifier 28.
Is output from. Further, even if a noise component exists in the pedestal portion of the input signal V _I , the noise component does not affect the video signal portion of the output signal V ₀ , and an accurate clamp operation is performed. . This is because, even if the noise component is held by the capacitor 25, the voltage across the capacitor 27 does not change significantly and the average value of the pedestal level of the input signal V _I continues to be maintained.

Next, the clamp circuit of the third embodiment will be described with reference to FIG. This clamp circuit is a so-called feed back clamp circuit. In FIG.
The signal input terminal 31 is a DC coupled amplifier 33 via an adder 32.
It is connected to the. The output side of the amplifier 33 is connected to the comparator 34 and the signal output terminal 35. A series circuit of a switch 37 and a constant current source 36 for operating the comparator 34 are connected to the comparator 34, and a DC power source 38 for supplying a clamp potential Ec ₃ is also connected to the comparator 34. In addition, the comparator 34 has a small-capacity capacitor 39
And a series circuit including a switch 40 and a capacitor 41 having a sufficiently larger capacity than the capacitor 39 are connected in parallel, and are also connected to the adder 32 via the switch 42. The switch 37 and the switches 40 and 42 are controlled by the clock signals φ and φ as shown in FIG. 3, respectively.

During the period T ₁ in which the clock signal φ is at a high level, the switch 37 is closed as shown in the figure, and the differential signal between the signal corresponding to the pedestal portion of the input signal V _I supplied from the amplifier 33 and the clamp potential Ec _3. The voltage Vd ₃ is output from the comparator 34,
A charge corresponding to this difference voltage Vd ₃ is accumulated in the capacitor 39. Further, the output signal V ₀ is fixed to the clamp potential Ec ₃ . Note that the switches 40 and 42 are opened in this period T ₁ . On the other hand, during the period T ₂ when the clock signal is at the high level, the switches 40 and 42 are closed, and the capacitors 39 and 41 are electrically connected by the switch 40, so that the capacitors 39 and 41 are respectively connected. The charge commensurate with the capacity is distributed. The voltage across the capacitor 41 is the average value of the differential voltage Vd ₃ . The voltage generated across the capacitor 41 is fed back to the adder 32 via the switches 40 and 42, and the video signal portion of the input signal V _I is level-shifted by the voltage across the capacitor 41,
The output signal V ₀ clamped at the clamp potential Ec ₃ is obtained. Further, even if a noise component exists in the pedestal portion of the input signal V _I , the noise component does not affect the video signal portion of the output signal V ₀ , and an accurate clamp operation is performed.

As described above, the first to the first using switch switch
According to each clamp circuit of the third embodiment, it is possible to perform an accurate clamp operation without being affected by noise. Moreover, since it is not necessary to use a large-capacity capacitor to obtain a large time constant, the entire clamp circuit can be integrated.

〔The invention's effect〕

As is apparent from the above description of the embodiment, the clamp circuit according to the present invention uses the switch capacitor including the first capacitor having a small capacity and the second capacitor having a sufficiently larger capacity than the capacitor. Therefore, a large time constant can be obtained without using a large capacity capacitor. Therefore, the entire clamp circuit can be integrated. In addition, it is possible to perform accurate clamp operation that is resistant to noise.

[Brief description of drawings]

1 is a circuit diagram showing a first embodiment of a clamp circuit according to the present invention, FIG. 2 is a circuit diagram showing a switch capacitor applied to the present invention, and FIG. 3 is a diagram showing an input signal and each clock signal. FIG. 4 is a waveform diagram showing an example, FIG. 4 is a circuit diagram showing a second embodiment of the clamp circuit according to the present invention, and FIG.
3 is a circuit diagram showing an embodiment of FIG. FIG. 6 is a circuit diagram showing an example of a conventional clamp circuit. 14,15,25,27,39,41 …… Capacitor 16,26 …… Transistor 40 …… Switch

Claims (3)

[Claims] 1. An input terminal to which a video signal is supplied, an output terminal from which a video signal is output, a first capacitor connected between the input terminal and the output terminal, and a first capacitor to the output terminal. A direct current power source connected via switch means for giving a clamp potential, and a second capacitor connected in parallel to the first capacitor via second switch means and having a larger capacity than the first capacitor. Comprising: The first switch means is turned on during a predetermined period of the pedestal period of the video signal to accumulate electric charge in the first capacitor according to a difference voltage between the pedestal level of the video signal and the clamp potential, and During the effective period of the video signal, the second switch means is turned on to connect the first capacitor and the second capacitor in parallel, Clamp circuit being characterized in that to obtain a video signal clamped to the clamp voltage. 2. An input terminal to which a video signal is supplied, an output terminal from which a video signal is output, a constant current source connected to the input terminal, and one end of which is connected to the input terminal via a first switch means. A first capacitor connected to the other end and grounded; a first capacitor having one end connected to the first capacitor via a second switch means and the other end having a larger capacity than the grounded first capacitor; And a differential amplifier to which the voltage across the second capacitor and the video signal from the input terminal are input, and the first switch means is turned on during a predetermined period of the pedestal period of the video signal. The first capacitor is caused to accumulate electric charge according to the pedestal level of the video signal, and the second switch means is turned on during the effective period of the video signal to make the first capacitor. The second connects the capacitor, clamp circuit, characterized in that from the output terminal to obtain a video signal which is maintained at an average value of the pedestal level. 3. An input terminal to which a video signal is supplied, an output terminal from which the video signal is output, an amplifier for amplifying the video signal from the input terminal, and one end of which is grounded via a first switch means. A direct current power supply for giving a clamp potential, a comparator for comparing the output from the amplifier and the output from the direct current power supply, a first capacitor having one end connected to the comparator and the other end grounded, Is connected to the first capacitor via the second switch means, and the other end is connected to the second capacitor having a larger capacity than the first capacitor, and the voltage from the second capacitor is connected to the third capacitor. An adder for adding to the amplifier via a switch means, and closing the first switch means for a predetermined period of the pedestal period of the video signal to cause the first capacitor to output the video signal. With charges according to the voltage difference between the Distal level the clamp potential, wherein said second switching means and the third by closing the switch means first capacitor to the validity period of the video signal the second
The clamp circuit is characterized in that the video signal clamped to the clamp potential is obtained from the output terminal by connecting to the capacitor.