JPH09233368A - Video signal clamp circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the clamp circuit not to need a high power supply voltage through a simple circuit configuration by utilizing a switching characteristic of an amplifier element so as to clamp a received video signal thereby providing an output of only a video signal component whose level is over the pedestal level. SOLUTION: At the reception of a clamp pulse, a MOS transistor(TR) M1 is conductive and a connecting point of drains of MOS TRs M1, M3 is held at a clamp reference bias voltage. When a smoothing pulse is received, a MOS TR 2 is conductive, a connecting point among sources of the TRs M2, M3 and an output terminal T2 is held to a clamp reference bias voltage Vref, which is equal to a pedestal level of a video signal. Thus, a synchronizing signal (horizontal synchronizing signal) included for a blanking period of the video signal and whose level is less than the pedestal level or noise is eliminated and only the image signal is extracted from the output terminal T2 as an output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal clamp circuit which is suitable for use in television equipment and the like and clamps a video signal.

[0002]

2. Description of the Related Art Generally, a video signal processing circuit used in a television receiver uses a clamp circuit at an input end in order to clamp a pedestal level of a video signal. FIG. 4 shows the configuration of such a conventional clamp circuit.

In FIG. 4, a video signal input from the input terminal Ta is input to the collector of the transistor Q2 and the collector and base of the transistor Q4 via the input capacitor C, and is also applied to the output terminal Tb.

The base and collector of the transistor Q1 are connected to each other, and the collector thereof is connected to the collector of the transistor Q3 and has a function equivalent to that of a diode. The emitter of the transistor Q1 is connected to the power supply (Vcc) via the resistor R1.

On the other hand, the transistor Q2 has an emitter connected to the power supply through the resistor R2 and a base connected to the base and collector of the transistor Q1.

A clamp reference bias voltage Vref is applied from the power source B to the base of the transistor Q3,
Its emitter is connected to the emitter of transistor Q4.

Further, a switch SW which is turned on only during the clamp period is connected to the emitters of the transistors Q3 and Q4, and a current source I is connected in series to the switch SW. As is apparent from the figure, the transistors Q3 and Q4 form a differential amplifier circuit, and the transistors Q1 and Q2 form a current mirror circuit.

In such a conventional clamp circuit, the switch SW is controlled so that it is turned on only during the clamp period, for example, by a control device (not shown). This switch SW
Is turned on, all the transistors Q1 to Q4 are turned on. Since the transistors Q3 and Q4 form a differential amplifier circuit,
It operates so that the base potentials of the transistors Q3 and Q4 become equal.

That is, during the clamp period in which the switch SW is on, when the clamp reference bias voltage Vref applied to the base of the transistor Q3 is higher than the base voltage of the transistor Q4, the transistor Q3 becomes conductive and the transistor Q4 becomes non-conductive. Becomes When transistor Q3 conducts, transistors Q1 and Q2 also conduct. Therefore, from the power supply (Vcc), the resistor R2 and the transistor Q2
A current flows through and charges the input capacitor C.

In addition, the base voltage of the transistor Q4 rises as the charging voltage rises due to the inflow current of the input capacitor C and becomes higher than the base voltage of the transistor Q3, that is, the clamp reference bias voltage Vref. At this time, the transistor Q4 becomes conductive and the transistor Q3 becomes non-conductive, and the charge of the input capacitor C is discharged through the transistor Q4, the switch SW, and the current source I.

In this way, the base voltage of the transistor Q4, that is, the output voltage is finally stabilized at the reference bias voltage Vref applied to the base of the transistor Q3.

In the period other than the clamp period in which the switch SW is off, the transistors Q1 to Q4 are off, the electric charge of the capacitor C is not discharged, and the voltage across both ends is held as it is.
Is output.

Therefore, the pedestal level of the input video signal is clamped to the reference bias voltage Vref at the base of the transistor Q3 and output at a constant level.

[0014]

However, the above-mentioned conventional clamp circuit has a large number of elements, and it is necessary to select one having the same electrical characteristics of each element, which has a disadvantage of lowering the yield. Also, transistors Q1 and Q
Since 3 and the transistors Q2 and Q4 are respectively connected in a hierarchical manner, a high power supply voltage is required to secure the required operating range. Therefore, each element also needs to have a high withstand voltage and the cost increases. Had become a factor to.

Therefore, the present invention has been made in view of the above problems, and a video signal clamp which has a simple circuit configuration, does not require a high power supply voltage, and is capable of equivalently increasing the operation range of a subsequent circuit. It is intended to provide a circuit.

[0016]

A video signal clamp circuit according to claim 1 of the present invention is a video signal clamp circuit for inputting and clamping a video signal, wherein a first amplifying element M1 for inputting a clamp pulse, To the second amplifying element M2 that inputs the smoothing pulse, the third amplifying element M3 that inputs the inverted smoothing pulse, the inverting means INV that inverts the smoothing pulse, and the first and second amplifying elements M1 and M2. It is composed of a reference power source B which supplies a clamp reference bias voltage.

That is, by utilizing the switching characteristics of the amplifying element, the input video signal is clamped, the synchronizing signal and noise included in the blanking period of the video signal are removed, and only the video signal component above the pedestal level is removed. Is output.

According to a second aspect of the present invention, the first, second and third amplifying elements M1, M2 and M3 are each composed of an N channel type MOS transistor.

According to a third aspect of the present invention, the first, second and third amplifying elements M1, M2 and M3 are each constituted by a P channel type MOS transistor.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing the configuration of a video signal clamp circuit of the present invention.

In FIG. 1, T1 is an input terminal for inputting a video signal, and C is an input capacitor. M1, M2, M
Reference numerals 3 are first, second and third amplifying elements, for example N
It is composed of channel type MOS transistors. MOS
The drain of the transistor M1 is a MOS transistor M
3 is connected to the drain and the input capacitor C, and a MOS
The source of the transistor M1 is the MOS transistor M2
Is connected to the drain of a reference power source B whose one end is grounded. The reference power source B supplies a clamp reference bias voltage Vref, and this Vref is set so that the pedestal level of the input video signal is maintained at a predetermined level. The gate of the MOS transistor M1 has a terminal T3 for inputting a clamp pulse.
And a terminal 4 for inputting a smoothing pulse is connected to the gate of the MOS transistor M2.

The source of the MOS transistor M3 is MO
It is connected to the source of the S-transistor M2 and is also connected to an output terminal T2 that outputs a clamped video signal. The output terminal of the inverter INV is connected to the gate of the MOS transistor M3. Inverter INV
The input end of is connected to the gate of the MOS transistor M2 and the terminal T4.

Next, the operation of the above configuration will be described with reference to the timing chart shown in FIG. Input terminal T
The video signal shown in FIG. At this time, when the clamp pulse shown in FIG. 2b is input to the gate of the MOS transistor M1, the MO
The S transistor M1 is turned on. As a result, the charge of the input capacitor C is charged and discharged, and the MOS transistor M1
And the drain connection point of M3 is clamp reference bias V
It becomes equal to ref, and the pedestal level P of the video signal coincides with this clamp reference bias voltage. The charge of the input capacitor C is held except during the clamp period.

A smoothing pulse having a width equal to the blanking period of the video signal shown in FIG. 2c is input to the gate of the MOS transistor M2, and the MOS transistor M2 becomes conductive. At this time, at the same time, the smoothing pulse is inverted and input to the gate of the MOS transistor M3 by the inverter INV, so that the MOS transistor M3 is turned off and the video signal does not appear at the output terminal T2. During this smoothing pulse period, the voltage levels of the MOS transistors M2 and M3 and the output terminal T2 are
It becomes equal to the clamp reference bias Vref.

That is, when the crank pulse is input, the MOS transistor M1 conducts, the connection point of the drains of the transistors M1 and M3 is held at the clamp reference bias voltage, and when the smoothing pulse is input, the MOS transistor M1.
2 becomes conductive, the connection points of the sources of the MOS transistors M2 and M3 and the output terminal T2 are held at the clamp reference bias voltage Vref, and become equal to the pedestal level of the video signal. Therefore, the sync signal (horizontal sync signal H) or noise below the pedestal level included in the blanking period of the video signal is removed, and only the video portion shown in FIG. 2d is taken out from the output terminal T2 as an output signal.

FIG. 3 is a block diagram showing the structure of another embodiment. This second embodiment is different from the embodiment of FIG. 1 in that it is composed of N-channel type MOS transistors.
The difference is that the transistors M1 to M3 are P-channel MOS transistors. Since the polarities of the clamp pulse and the smoothing pulse are only inverted and input, and the operation is the same as the operation shown in FIG. 1, the description thereof will be omitted.

Therefore, by using the N-channel or P-channel MOS transistor, it can be used according to the characteristics of other video signal processing circuits.

[0028]

As described above, according to the video signal clamp circuit of the present invention as defined in claims 1 to 3, a simple circuit configuration having a very small number of elements and parts and a power supply voltage can be provided. Also has the advantage that it can be reduced compared to the conventional circuit configuration.

Further, since the sync signal and noise below the pedestal level included in the blanking period of the video signal are removed, the input range of the circuit connected after this clamp circuit is adjusted by the amplitude of the sync signal. There is a benefit equivalent to increasing the signal amplitude to be spread and processed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a video signal clamp circuit of the present invention.

FIG. 2 is a timing chart showing waveforms of essential parts of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional clamp circuit.

[Explanation of symbols]

 M1 to M3 MOS transistor (amplifying element) INV Inverter B Reference power supply Vref Reference voltage

Claims (3)

[Claims] 1. A video signal clamp circuit for inputting and clamping a video signal, wherein a first amplifying element for inputting a clamp pulse, a second amplifying element for inputting a smoothing pulse, and the inverted smoothing pulse are inputted. A video signal clamp circuit, comprising: a third amplifying element, an inverting means for inverting the smoothing pulse, and a reference power source for applying a clamp reference bias voltage to the first and second amplifying elements. 2. The first, second and third amplifying elements are respectively N
The video signal clamp circuit according to claim 1, wherein the video signal clamp circuit includes a channel type MOS transistor. 3. The first, second and third amplifying elements are respectively P
The video signal clamp circuit according to claim 1, wherein the video signal clamp circuit includes a channel type MOS transistor.