JPH11112345A - Agc circuit for video - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an AGC circuit for video which can extend an input dynamic range much more at the time of a low power voltage operation. SOLUTION: A voltage dividing means 6 constituted of the series circuit of plural resistors, a switch means 7 having plural N channel MOS transistor switches which are changed over in accordance with a control signal by receiving the output of the means 6 and which output the signal and a sync tip clamping circuit 4 clamping lowest potential in the input of the voltage dividing means 6 to ground potential are provided. Thus, the dynamic range in the input of the voltage dividing means 6 can be enlarged until the plural N channel MOS transistor switches of the switch circuit 7 can keep conduction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a video AGC circuit, and more particularly to a video AGC circuit suitable for a low power supply voltage operation.

[0002]

2. Description of the Related Art AGC for video conventionally used
The circuit will be described with reference to FIG. First, terminal 1
Is supplied to the input side of the gain control circuit 16 via the capacitor 3. Gain control circuit 16
Is output from the analog-to-digital conversion means 9 (hereinafter referred to as
After being converted into digital data by “A / D conversion means”, the digital data is supplied to an amplitude detection circuit 10, and a gain control signal corresponding to the amplitude of the input video signal is supplied to a control input 11 of a gain control circuit 16. Return to.

Here, the gain control signal is set in the output data of the A / D converter 9 so that the amplitude of the video signal corresponding to the output data becomes constant.
The entire circuit shown in FIG. 4 operates as an AGC that operates to keep the amplitude of a video signal corresponding to digital data output to the terminal 12 constant. Note that the resistor 2 is a terminating resistor, and the clamp 4 is for clamping an input video signal in accordance with the input range of the gain control circuit 16.

Next, the configuration of the gain control circuit 16 will be described.
This will be described with reference to FIG. FIG. 5 is a block diagram of the gain control circuit 16 in FIG. In FIG. 5, the selector 7
5 converts the video signal supplied to the terminal 5 into the first, second, third, and fourth current conversion circuits 91, 92, 93, and 94 according to the gain control signal supplied to the terminal 11. Is selectively output for any one of The gain control signal supplied to the terminal 11 is also supplied to first, second, third, and fourth current conversion circuits 91, 92, 93, and 94. However, the current conversion circuit for setting this operation state is the same as the current conversion circuit for receiving the video signal selectively supplied from the selector 75.

Since the conductances of the first, second, third, and fourth current conversion circuits 91, 92, 93, and 94 are set to different values, respectively,
Second, third, and fourth current conversion circuits 91, 92, 93, 9
The current supplied to the input of the voltage conversion circuit 78 to which the output of the terminal No. 4 is connected in common is the signal voltage of the video signal supplied to the terminal 5, and the first voltage selected solely by the gain control signal supplied to the terminal 11. Second, third, and fourth current conversion circuits 9
1, 92, 93, 94 multiplied by the conductance of one of them. Voltage conversion circuit 78 converts the current supplied to the input into a voltage again and outputs the voltage to terminal 8.

From the above operation, the block diagram of the gain control circuit 16 shown in FIG. 5 shows that the video signal supplied to the terminal 5 is amplified by a gain corresponding to the gain control signal supplied to the terminal 11 and It operates as an output variable gain amplifier. The current supply circuit 76 and the bias circuit 79
Are the first, second, third, and fourth current conversion circuits 91, 9
2, 93 and 94 and a voltage conversion circuit 78.

Next, referring to FIG. 6, gain control circuit 16
Will be described in more detail. First current conversion circuit 91
Is selectively operated by the gain control signal and determined by the current flowing through the second constant current source 19, the differential circuit including the first and second transistors 30 and 31 and the second resistor 39. And fourth and fourth transistors 22 and 23 which output a current equal to the current to be applied. First
The second transistors 30, 31 and the third and fourth transistors 22, 23 have the same size.

The first, second, third, and fourth resistors 39, 40, 41, and 42 in the first to fourth current conversion circuits are set to different values. The voltage conversion circuit 78 includes the seventeenth, eighteenth, nineteenth, and twentieth transistors 44, 4
It comprises a voltage follower composed of 5, 46, 47 and a 57th constant number of radio waves, and a current mirror circuit load resistor 43 composed of 21st to 29th transistors 48 to 56.

The actual operation will be described for the case where the first current conversion circuit 91 is selected by the gain control signal. The video signal is applied to the gate of the first transistor 30 and the output of the fixed bias circuit 79 is applied to the gate of the second transistor 31, respectively.
A current determined by the first constant current source 19 flows through the fourth transistors 22 and 23. As a result, the differential circuit constituted by the first and second transistors 30 and 31 and the first resistor 39 enters an operating state, and the first and second transistors 30 and 31 receive the first and second transistors from the drains of the first and second transistors 30 and 31, respectively. And outputs an output current corresponding to the difference voltage applied between the gates of the transistors 30 and 31. That is, the first current conversion circuit is in the operating state in this case.

On the other hand, the fifth to sixteenth transistors 24 to
Since the power supply voltage is supplied to the gates of the transistors 29 and 32 to 37, all of these transistors are in the cut-off state, so that the third, fourth, seventh, eighth, eleventh, and twelfth transistors 32 , 33, 34, 35, 36, and 37, no current is output. Therefore, the second, third, and fourth current conversion circuits 92, 93, and 94 do not operate, and
Only the first current conversion circuit 91 is activated, only this output current is supplied to the voltage conversion circuit 78, converted into a voltage again by the load resistor 43, and output from the terminal 8.

The conventional gain control circuit 16 shown in FIG.
The upper limit of the input dynamic range is that both the differential circuit and the transistor that supplies a constant current to the differential circuit are in saturation, that is, the drain-source voltage of these transistors is smaller than the gate-source voltage. Is determined within a range that keeps a constant state, which is determined by the gates of the transistors that supply the constant current, the transistors that make up the differential circuit, and the transistors that receive the output of the differential circuit.
It is equal to the sum of the source-to-source voltages minus the power supply voltage. The threshold voltage of all these transistors is VT
If the power supply voltage is assumed to be VDD and the gate-source voltage of the saturated transistor is always higher than VT, the upper limit of the input dynamic range of the conventional gain control circuit 16 shown in FIG. -3) (VT).

[0012]

In the above-mentioned conventional AGC circuit for video, the upper limit of the input dynamic range of the gain control circuit for varying the gain cannot be made larger than "VDD-3.VT". Therefore, when a low voltage operation of VDD of 3 V is performed, the upper limit of the input dynamic range is set to 3−3 × 0.7 = 0.9 VPP by using 0.7 V that is normally given as the threshold voltage of the MOS transistor. Becomes

However, since the typical amplitude of a standard video signal is 1 VPP, when this conventional video AGC circuit is operated at a low voltage of VDD = 3 V, the standard video signal is supplied to the standard video signal. Even the amplitude of a video signal exceeds the upper limit of the input dynamic range, and there is a problem that the output of the video signal causes waveform distortion such as clipping.

The present invention has been made in view of the above problems, and an object thereof is to expand the input dynamic range at the time of low power supply voltage operation as compared with the conventional one. An object of the present invention is to provide an AGC circuit for video.

[0015]

According to the present invention, there is provided a video A.
The GC circuit is a series circuit including a plurality of resistors having one end directly connected to the input and the other end grounded, and a plurality of resistors having a common connection point of adjacently connected resistors among the plurality of resistors as an output. A voltage dividing means having a pressure output, and a drain for receiving the plurality of divided outputs of the voltage dividing means and selecting and outputting the plurality of divided outputs of the voltage dividing means in accordance with a control signal. Switching means having a plurality of N-channel MOS transistor switches to be connected, analog-to-digital conversion means for receiving an output of the switching means, converting the output into a digital signal, and receiving the output of the analog-to-digital conversion means; An amplitude detection circuit for feeding back the control signal to the switching means; and a system commonly connected to the input of the voltage dividing means for clamping the lowest potential of the input to a substantially ground potential. Characterized by comprising a click tip clamp circuit, a (claim 1), which makes it possible to achieve the above object.

In the video AGC circuit according to the present invention, the switching means drives a plurality of N-channel MOS transistor switches in response to a pump-up circuit, an output of the pump-up circuit and the control signal. (Claim 2).

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a video AG according to the present invention will be described.
An embodiment of the C circuit will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of a video AGC circuit according to the present invention. The video signal input to terminal 1 is input to one end of voltage dividing means 6 via capacitor 3. The capacitor 3, together with the clamp 4 connected to the input of the voltage dividing means 6, holds the leading end of the synchronizing signal, which is the lowest potential portion of the positive polarity video signal at the input of the voltage dividing means 6, at substantially the ground potential. A sync tip clamp for clamping the signal voltage at the input of the voltage dividing means 6 so that it always has a positive polarity with respect to the ground potential is formed.

The clamped video signal supplied to the voltage dividing means 6 is divided and outputted at a plurality of divided voltage outputs V1 to Vn (n is an integer) at mutually different voltage dividing ratios and supplied to the switching means 7. The switching means 7 selects only one of the outputs V1 to Vn according to the control signal 11 fed back from the amplitude detection circuit 10 and outputs the selected output to the A / D conversion means 9.

Next, the operation of the voltage dividing means 6 and the switching means 7 will be described in detail with reference to FIG. The pressure dividing means 6 is R
A series circuit of a plurality of resistors 1 to Rn (n is an integer),
The division ratio of the input to the plurality of divided outputs V1 to Vn is as follows: Is set.

These divided voltage outputs V1 to Vn are obtained by decoding the control signals via the decoder 100 into the decoded signals C1 to Cn.
Only one is selected by transistor switches S1 to Sn composed of N-channel MOSFETs controlled by Cn, and is output to the output of the switching means 7. Usually, low-level and high-level voltages close to 0 V or VDD are applied to C1 to Cn.

Here, the conditions under which the voltage dividing means 6 and the switching means 7 in FIG. 2 operate normally are determined within a range in which the conduction or non-conduction state of the transistor switches S1 to Sn of the switching circuit 7 can be controlled. The severe condition is that if the voltage at terminal 5 is VT at the threshold of transistor switch S1,
This is the case when it has risen to DD-VT. By the way, since the video signal given to the terminal 5 oscillates more positively than the ground potential, the voltage dividing means 6 and the switching means 7 are eventually turned on.
, It is possible to input a video signal having an amplitude of approximately VDD−VTh, where VDD = 3V and VTh =
With a voltage of 0.7 V, a video signal having an amplitude up to 2.3 VPP can be input.

(Second Embodiment) Next, a second embodiment of the video AGC circuit according to the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 3 has a pump-up circuit 101 for further increasing the output voltage on the high potential side of the outputs C1 to Cn of the decoder 100 in FIG. 2 above VDD. By having the pump-up circuit 101, even if the voltage applied to the terminal 5 rises to almost VDD, the conduction state of S1 to Sn can be ensured, so that the input dynamic range is expanded to almost VDD. It is also possible to reduce the ON resistance in the conductive state of the transistor switches S1 to Sn.
The cutoff frequency limited by the resistance and the parasitic capacitance associated with the circuit can be increased. Therefore, it is possible to process a wider band signal.

[0025]

As described above, the video AGC circuit according to the present invention has one end directly connected to the input, and
A voltage dividing means having a plurality of divided outputs having a common connection point of resistors connected adjacently in the plurality of resistors, the voltage dividing means being a series circuit of a plurality of resistors each having the other end grounded; Switching means having a plurality of N-channel MOS transistors for receiving the plurality of divided outputs of the means and selecting and outputting the plurality of divided outputs of the voltage dividing means in response to a control signal; Connected in common to said inputs of the means;
Since a sync tip clamp circuit for clamping the lowest potential of the input to substantially the ground potential is provided, the input dynamic range at the input is assured by the conduction / non-conduction state of the plurality of N-channel MOS transistors of the switching means. It is possible to expand to the limit where possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a video AGC circuit according to the present invention.

FIG. 2 is a circuit diagram for describing in detail a first embodiment of a video AGC circuit according to the present invention.

FIG. 3 is a circuit diagram of a second embodiment of a video AGC circuit according to the present invention.

FIG. 4 is a block diagram of a conventional video AGC circuit.

FIG. 5 is a block diagram of a gain control circuit in the conventional video AGC circuit shown in FIG.

6 is a circuit diagram of a gain control circuit in the conventional video AGC circuit shown in FIG.

[Explanation of symbols]

 1, 5, 8, 11, 12 Terminal 2 Terminating resistor 3 Capacitor 4 Clamp 6 Voltage dividing means 7 Switching means 9 A / D conversion means 10 Amplitude detection circuit 16 Gain control circuit 75 Selector 76 Current supply circuit 78 Voltage conversion circuit 79 Bias Circuits 91, 92, 93, 94 Current conversion circuits 21-37, 44-56 MOS transistors 39-43 Resistors 19, 57 Constant current sources 64-71 Switches 100 Decoders 101 Pump-up circuits

Claims (2)

[Claims] 1. A series circuit comprising a plurality of resistors having one end directly connected to an input and the other end grounded, the plurality of resistors having a common connection point of adjacently connected resistors among the plurality of resistors as an output. A voltage dividing means having a divided voltage output, and a drain which receives the plurality of divided voltage outputs of the voltage dividing means and selects and outputs the plurality of divided voltage outputs of the voltage dividing means according to a control signal. N channels M connected to
Switching means having an OS transistor switch; analog-to-digital conversion means for receiving the output of the switching means and converting it to a digital signal; and outputting the digital-to-digital signal; A video AG comprising: an amplitude detection circuit for feeding back a signal; and a sync tip clamp circuit commonly connected to the input of the voltage dividing means and clamping a minimum potential of the input to a substantially ground potential.
C circuit. 2. The switching means includes a pump-up circuit,
Receiving the output of the pump-up circuit and the control signal,
2. The video AGC circuit according to claim 1, further comprising a decoder circuit for driving said plurality of N-channel MOS transistor switches.