JP2957831B2 - Peak hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak hold circuit for accurately holding a peak voltage of an incoming signal.

[0002]

2. Description of the Related Art In the United States, a television receiver having a built-in closed caption function for displaying subtitles of a broadcaster in real time so that a hearing-impaired person can enjoy television broadcasting is sold. Caption data for displaying a caption is superimposed on the 21st horizontal scanning period (hereinafter referred to as 21H) in the vertical retrace period of the video signal. See Figure 5 for details.
As shown in the figure, the run-in clock indicating the presence / absence of caption data and the caption data indicating the subtitle content are 2
1H. To decode the caption data, clamp the pedestal of the video signal to the reference voltage, detect the peak voltage at the top of the run-in clock, and then slice the caption data at the midpoint voltage indicated by the dashed line between the reference voltage and the peak voltage. Is generated by generating multi-bit data consisting of "0" and "1", and taking the multi-bit data into a microcomputer.
Then, by performing signal processing for displaying subtitles on the decoding result of the microcomputer, characters can be viewed on a television screen. Here, a conventional circuit for detecting and holding the peak voltage at the uppermost part of the run-in clock will be described with reference to FIG. The video signal has a positive polarity, and its pedestal is clamped at a certain voltage.

In FIG. 3, reference numeral (1) denotes a comparator, to which a run-in clock superimposed on the video signal 21H is applied to a non-inverting input terminal, and to the inverting input terminal, the uppermost part of the run-in clock immediately before. The peak voltage is fed back from an output terminal of an operational amplifier described later. The comparator (1) generates a high level (5 volts) when the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal. Conversely, the voltage at the non-inverting input terminal becomes higher than the voltage at the inverting input terminal. Generates low level (0 volt) when small. (2) is an inverter for inverting the output voltage of the comparator (1).
(3) is a P-channel type switching transistor, the gate is connected to the output terminal of the inverter (2), the source is connected to the power supply Vdd (5 volts), and the peak voltage at the top of the current run-in clock is immediately before. When the output voltage of the inverter (2) becomes low level, that is, when the output voltage of the inverter (2) becomes low level. The switching transistor (3) has a parasitic capacitance (4) between the gate and the drain in terms of structure, and the parasitic capacitance (4) is charged with 5 volts with the conduction of the switching transistor (3). Will be (5) and (6) are a resistor and a capacitor connected in series between the drain of the switching transistor (3) and the ground, and integrate the output current when the switching transistor (3) is turned on. (7) is an operational amplifier, in which a non-inverting input terminal is applied with an integrated voltage generated at a connection point of a resistor (5) and a capacitor (6), and an inverting input terminal has a voltage at an output terminal equal to the integrated voltage. The feedback is performed in the same manner as above to generate a peak voltage from the output terminal. That is, the operational amplifier (7)
Updates the output voltage when the peak voltage at the top of the run-in clock is higher than the previous peak voltage, and updates the output voltage when the peak voltage at the top of the run-in clock is lower than the previous peak voltage. It holds the output voltage. The peak voltage generated from the output terminal of the operational amplifier (7) is also fed back to the inverting input terminal of the comparator (1). The voltage is compared with a peak voltage that is updated as needed immediately before. FIG. 4 is a time chart showing the waveforms of the respective parts in FIG. 3; the input waveform (dot-dash line) of the comparator (1), the output waveform of the comparator (1), the output waveform of the inverter (2), 3) shows the output waveform (solid line).

[0004]

However, the peak voltage at the top of the run-in clock applied to the non-inverting input terminal of the comparator (1) is the peak voltage fed back to the inverting input terminal of the comparator (1). When the state changes from a larger state to a smaller state, as the output voltage of the inverter (2) is inverted to a high level, the charge stored in the parasitic capacitance (4) is shifted from 10 volts on the a side to 5 volts on the b side, and switching is performed. With the cutoff of the transistor (3), the accumulated charge of the parasitic capacitance (4) is discharged and integrated through the resistor (5) and the capacitor (6). Therefore, the integrated voltage ΔV corresponding to the accumulated charge of the parasitic capacitance (4) is applied to the non-inverting input terminal of the operational amplifier (7), and as a result, the peak voltage fed back to the comparator (1) becomes a broken line. However, there is a problem that an error is included by + ΔV from the original peak voltage shown in FIG.

For example, as shown in FIG. 6, when the peak voltage of a video signal being conveyed is extremely low due to adverse effects of location conditions, weather conditions, etc., the peak voltage at the top of the run-in clock is + ΔV. Including the error of
The slice voltage obtained by using the reference voltage and the peak voltage in the subsequent circuit abnormally rises, and the caption data
Data could not be sliced and incorrect data was transferred to the microcomputer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a peak hold circuit which can accurately hold an incoming signal even if its peak voltage is extremely small.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a feature thereof is a peak hold circuit for detecting and holding a peak voltage of an incoming signal. A comparator in which the incoming signal is applied to one input terminal and a peak voltage up to immediately before is applied to the other input terminal, and the comparator when the incoming signal becomes larger than the previous peak voltage. A first switching transistor having a first parasitic capacitance between input and output terminals, to which the output voltage of the first switching transistor is applied, an integrator for integrating an output current when the first switching transistor is conductive, and one input terminal An operational amplifier that receives the integrated voltage of the integrator, feeds back the output voltage to the other input terminal of the comparator, and conducts simultaneously with the first switching transistor. A second switching transistor having a second parasitic capacitance equal to the first parasitic capacitance between terminals, wherein the first and second parasitic capacitances are set when the incoming signal becomes smaller than the immediately preceding peak voltage. By operating the integrator based on the above, the fluctuation of the peak voltage is prevented.

[0008]

According to the present invention, even if the incoming signal becomes smaller than the previous peak voltage, the peak is achieved by operating the integrator based on the first and second parasitic capacitances of the first and second switching transistors. Voltage fluctuation can be prevented.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 shows a peak hold circuit according to the present invention. The video signal has a positive polarity, and its pedestal is clamped at a certain voltage. 1 and 3 are denoted by the same reference numerals.

In FIG. 1, (8) is an N-channel type second switching transistor, the gate is connected to the output terminal of the comparator (1), and the drain is connected via a resistor (9) to the first switching transistor (8). 3) is connected to the drain, and the source is grounded. The second switching transistor (8) has a second parasitic capacitance (10) between the gate and the drain, which is equal to the first parasitic capacitance (4). And the second switching transistor (8)
When the peak voltage at the top of the run-in clock applied to the non-inverting input terminal of the comparator (1) becomes higher than the peak voltage fed back to the inverting input terminal, ie, the comparator (1)
When the output voltage of the first switching transistor becomes a high level, it is conducted together with the first switching transistor (3).

The operation of FIG. 1 will be described below with reference to the time chart of FIG. In FIG. 2, the input waveform (dot-dash line) of the comparator (1), the output waveform of the comparator (1), the output waveform of the inverter (2), and the output waveform (solid line) of the operational amplifier (7) are the same. Shown on the time axis. Also, as shown in FIGS. 5 and 6, the amplitudes of the run-in clocks in a plurality of periods are the same, but the amplitude of the input waveform is changed for the sake of simplicity in explaining the operation of FIG.

First, at time t0, when the input waveform indicating the run-in clock starts to rise, a high level is output from the comparator (1), and the first and second switching transistors (3) and (8) are both Conduct. Then, the first
The output current flowing through the switching transistor (3) is integrated by flowing through the resistor (5) and the capacitor (6), and the integrated voltage at this time is applied to the operational amplifier (7). Then, an output voltage equal to the integral voltage is obtained from the operational amplifier (7), that is, an output waveform that rises following the input waveform is obtained from the operational amplifier (7), and is fed back to the comparator (1) as a peak voltage. You. On the other hand, with the conduction of the first switching transistor (3), the a side of the first parasitic capacitance (4) is charged to 5 volts and the b side is charged to 0 volt, and with the conduction of the second switching transistor (8), 2 The parasitic capacitance (10) is charged to 5 volts on the a 'side and 0 volt on the b' side.

Thereafter, at time t1, the comparator (1)
When the input waveform applied to the non-inverting input terminal is smaller than the peak voltage fed back to the inverting input terminal, a low level is output from the comparator (1), and the first and second switching transistors (3) (8) ) Both cut off. At this time, the a side of the first parasitic capacitance (4) is 10 volts b
The side is shifted to 5 volts, the a ′ side of the second parasitic capacitance (10) is shifted to 0 volts, and the b ′ side is shifted to −5 volts.
Then, the accumulated charge of the first parasitic capacitance (4) is discharged in a direction in which the capacitor (6) charges, and the second parasitic capacitance (1) is discharged.
The accumulated charge 0) is discharged in a direction in which the capacitor (6) discharges. Therefore, the first and second parasitic capacitances (4) (1
Since the accumulated charges of 0) cancel each other, the integrated voltage generated at the connection point of the resistor (5) and the capacitor (6) does not change, and the peak voltage fed back from the operational amplifier (7) to the comparator (1). Is maintained at the level at time t1.

Thereafter, at times t2 and t4, when the input waveform applied to the non-inverting input terminal of the comparator (1) becomes larger than the peak voltage fed back to the inverting input terminal,
Similarly, the peak voltage fed back from the operational amplifier (7) to the comparator (1) rises following the input voltage. Similarly, at times t3 and t5, when the input waveform applied to the non-inverting input terminal of the comparator (1) becomes smaller than the peak voltage fed back to the inverting input terminal, the operational amplifier (7) similarly performs comparison. The peak voltage fed back to the device (1) is maintained at the level at times t3 and t5.

Thus, in order to obtain the peak voltage at the uppermost part of the run-in clock, it is possible to prevent the integrated voltage corresponding to the charge accumulated in the first parasitic capacitance (4) from being superimposed on the peak voltage as an error voltage. Therefore, the caption data can be reliably sliced based on the accurate peak voltage, and the subtitle information indicated by the caption data can be correctly decoded by the microcomputer. In particular, the present invention can accurately detect the peak voltage of the run-in clock even when the amplitude of the video signal becomes extremely small due to a combination of adverse factors such as weather conditions and location conditions.

[0016]

According to the present invention, the integrator is operated based on the first and second parasitic capacitances of the first and second switching transistors even if the incoming signal becomes smaller than the previous peak voltage. This has the advantage that the error voltage can be prevented from being superimposed on the peak voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing a peak hold circuit of the present invention.

FIG. 2 is a time chart showing waveforms of respective parts in FIG.

FIG. 3 is a diagram showing a conventional peak hold circuit.

FIG. 4 is a time chart showing waveforms of respective parts in FIG. 3;

FIG. 5 is a diagram showing a video signal on which typical caption information is superimposed.

FIG. 6 is a diagram showing a video signal on which caption information having an extremely small amplitude is superimposed.

[Explanation of symbols]

 (1) Comparator (3) First switching transistor (4) First parasitic capacitance (5) Resistance (6) Capacitor (7) Operational amplifier (8) Second switching transistor (10) Second parasitic capacitance

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaya Ota 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Shusaku Terawaki 2-18-18 Keihanhondori, Moriguchi-shi, Osaka (56) References JP-A-4-242321 (JP, A) JP-A-4-4680 (JP, A) JP-A-3-110374 (JP, U) (58) Fields surveyed ( Int.Cl. ⁶ , DB name) G01R 19/00-19/32 G11C 27/00-27/04

Claims (2)

(57) [Claims] 1. A peak hold circuit for detecting and holding a peak voltage of an incoming signal, comprising: a comparator in which the incoming signal is applied to one input terminal and a peak voltage immediately before is applied to the other input terminal; A first switching transistor having a first parasitic capacitance between input and output terminals, to which the output voltage of the comparator when the incoming signal has become higher than the previous peak voltage is applied and is conductive; An integrator for integrating an output current when the switching transistor is turned on; an operational amplifier to which an integrated voltage of the integrator is applied to one input terminal, and an output voltage fed back to the other input terminal of the comparator; Conducting simultaneously with the first switching transistor,
A second switching transistor having a second parasitic capacitance equal to the first parasitic capacitance between the input and output terminals, wherein the first and second parasitic capacitors are provided when the incoming signal becomes smaller than the immediately preceding peak voltage. A peak hold circuit, wherein fluctuation of a peak voltage is prevented by operating the integrator based on capacitance. 2. The peak hold circuit according to claim 1, wherein the first and second switching transistors have different polarities and are connected in series between the first and second power supplies.