JP3263557B2 - Character data slice circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character data slicing circuit suitable for accurately extracting character data such as caption data superimposed in a specific horizontal scanning period of a video signal.

[0002]

2. Description of the Related Art At present, in the United States, a so-called closed caption system capable of displaying or not displaying character information on a television screen according to a user's desire is implemented for the purpose of a deaf-mute person. The closed caption system superimposes digital data in which character information is coded in a 21st horizontal scanning period (hereinafter referred to as 21H) of an odd field forming a video signal, and is transmitted in this state from, for example, a broadcasting station. By decoding the superimposed digital data on the television receiver side, it can be displayed on a television screen.

FIG. 3 shows data superimposed on 21H. In FIG. 3, a run-in clock of 7 cycles, a 3-bit start bit fixed to “001”, and 16-bit caption data (digital data obtained by encoding character information) are serially stored in 21H. It is superimposed. Here, the run-in clock is 503 KH.
z is a signal for notifying that the caption data is superimposed on 21H, and when the period of generation of each bit of the start bit is one cycle, this one cycle is 503 KHz similarly to the run-in clock. Assuming that the generation period of each bit of the caption data is one cycle, this one cycle is also 503 like the run-in clock.
KHz. The run-in clock, the start bit, and the caption data have a pedestal level of a video signal of Vd by a clamp circuit described later.
Since Vdd / 2 is clamped at d / 2, it is superimposed so that Vdd / 2 becomes a low level.

In order to decode caption data superimposed on a video signal and display it on a television screen, it is necessary to extract caption data composed of binary data "0" and "1" from the video signal without error. Therefore, a conventional caption data slice circuit is shown in FIG. It is assumed that the circuit in FIG. 2 is integrated inside the microcomputer.

In FIG. 2, (1) is a video signal input terminal to which a composite video signal is applied via a coupling capacitor (2) externally connected to a microcomputer. After the composite video signal is applied to the video signal input terminal (1), it is applied to the clamp circuit (3), and the pedestal level of the composite video signal is clamped to Vdd / 2 by the clamp circuit (3). still,
An example of the above-described clamp circuit (3) is described in Japanese Patent Application No. 5-48041 filed by the present applicant, and the internal description thereof is omitted. (4) (5) (6)
(7) is a resistor connected in series between the power supply Vdd and the power supply Vdd / 2. Here, one end (the lowest potential of the series resistance) of the resistor (7) is connected to Vdd / 2 because the pedestal level of the composite video signal is Vdd / 2,
This is because the caption data is superimposed on the composite video signal with Vdd / 2 as a low level.

(8), (9) and (10) are transmission gates (switch circuits), one ends of which are connected to respective connection points of resistors (4), (5), (6) and (7), and the other ends are common. It is connected. Any one of the transmission gates (8), (9), and (10) opens the gate according to the decoding output of the decoder described later. (11) is a comparator that operates only during the period of 21H, a composite video signal output from the clamp circuit (3) is applied to a + (non-inverting input) terminal, and a-(inverting input) terminal is a transmission gate. (8) It is connected to the common connection point at the other end of (9) and (10). That is, the negative terminal of the comparator (11) has a reference point voltage at a connection point of the resistors (4), (5), (6), and (7) connected to any one of the transmission gates whose gates are opened. Applied.

Reference numeral (12) denotes a register having a 2-bit structure, and control data b0 and b1 for opening any one of the transmission gates (8), (9) and (10).
Is set via the internal bus (13). Incidentally, the two bits of the control data are the minimum number of bits necessary to select any one of the three transmission gates (8), (9), and (10). (14) is the above-mentioned decoder, and the control data b set in the register (12)
Decode 0 and b1 and transmit gate (8)
(9) A gate control signal which becomes high level is output to any one of the control terminals of (10).

(15) is a judging means, and the comparator (1)
This is to determine whether the comparison output of 1) is normal. Specifically, the condition is that the reference voltage selected between the power supply Vdd and the power supply Vdd / 2 is set to a level lower than the high level of the run-in clock, the start bit, and the caption data. When the reference voltage is set in this condition, the comparator (11) outputs “1” when each bit of the caption data is at a high level, and outputs “0” when each bit of the caption data is at a low level. The contents of 16 bits are extracted without error.
Therefore, the determination means (15) determines whether the start bit “001” is correctly output from the comparator (11), or when the 16-bit caption data is divided into 8 bits, the two 8-bit data are determined. It is determined whether the parity bit allocated to the most significant bit is normal or not, and only when it is determined that the parity bit is abnormal, the register (1
The control data b0 and b1 in 2) are rewritten. That is, the information superimposed on 21H of the composite video signal may be superimposed with the amplitude fluctuating for some reason. For example, when the high level of the start bit becomes lower than the reference voltage, “001” should be output from the comparator (11), but “000” is actually output. . In these cases, a lower reference voltage is required,
Control data b0 and b1 for opening a transmission gate at a position where a reference voltage lower than the current reference voltage can be generated are set in the register (12). The determining means (15) is software means for determining the comparison output of the comparator (11) by program processing. Based on the determination result of the determining means (15), the register (12) is connected via the internal bus (13). ) Are set with control data b0 and b1. It should be noted that there is no problem even if the determining means (15) is configured as hardware. In this case, the value of the register (12) may be directly changed by the output of the determining means (15).

With the above configuration, since the reference voltage can be changed in accordance with the superimposition state of the information on the video signal 21H, correct caption data can be extracted from the comparator (11).

[0010]

Now, in the above-mentioned section of the prior art, it has been described that correct caption data can be extracted from the comparator (11). The case where it is determined that there is no abnormality in the output of the comparator (11) and the case where the value of the register (12) is changed by the output of the determination means (15) when there is an abnormality in the output of the comparator (11). Therefore, even when the output of the comparator (11) is found to be abnormal and the reference voltage is changed, the comparator (11) outputs erroneous caption data even for a short time. There is a problem that sampling is performed and an incorrect character is displayed. This problem is caused by fixing the power supply Vdd (the highest potential of the series resistance) connected to one end of the resistor (4).

Accordingly, the present invention provides a character data which can extract more correct character data than before even if the amplitude of character data such as caption data to be superimposed in a specific horizontal scanning period of a video signal fluctuates for some reason. It is an object to provide a data slicing circuit.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned problem, and is characterized in that a specific one of video signals whose pedestal level is clamped at a predetermined potential is provided. A peak hold circuit for holding a peak value of character data superimposed during a horizontal scanning period, and a plurality of resistors connected in series between an output of the peak hold circuit and a pedestal level of the video signal clamped and the same voltage. A plurality of switch circuits having one terminal connected to each connection point of the plurality of resistors and the other terminal commonly connected, any one of which selectively forms a signal path, and the plurality of switch circuits The divided voltage obtained from the connection point of the plurality of resistors is applied to one input as a reference voltage via any one of the above, and the video signal clamped to the other input is applied. Comprising a 較器, and the character data from the video signal is that withdrawn as digital data of "0" or "1".

[0013]

According to the present invention, the reference voltage applied to one input of the comparator is obtained from each connection point of a plurality of resistors connected in series. A peak hold circuit for holding a peak value of character data superimposed in one horizontal scanning period is provided. Thus, when the amplitude of the character data changes, the peak value also changes, so that the reference voltage also changes instantaneously in accordance with the amplitude change of the character data, so that the reference voltage is always correct without waiting for the judgment output of the judging means. Character data can be extracted from the video signal.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a character data slicing circuit according to the present invention. It is assumed that the circuit in FIG. 1 is integrated inside the microcomputer similarly to the circuit in FIG. In FIG. 1, the same parts as those in FIG.
The description is omitted.

In FIG. 1, (16) is a comparator,
A composite video signal CVIDEO whose pedestal level is clamped to Vdd / 2 is applied to the + terminal.
Reference numeral (17) denotes a NAND gate. A comparison output of the comparator (16) is applied to one input, and a signal LN21 that is at a high level only during a 21H period of the composite video signal is applied to the other input. (18) and (19) are P-channel MOS transistors (hereinafter, referred to as PMOS transistors). The gate is commonly connected to the output of the NAND gate (17), the drain and source paths are connected in series, and the PMOS transistor (18) Source is power supply Vd
d. In addition, the PMOS transistor (1
8) The drain connection point of (19) is connected to the negative terminal of the comparator (16) via the resistor (20). (21)
(22) are resistors and capacitors, respectively, which are connected in series between the drain of the PMOS transistor (19) and the power supply Vdd / 2. (23) is a resistor, which is connected in parallel with the capacitor (22). Here, the resistance (2
1) and the capacitor (22) form a charging path when the PMOS transistors (18) and (19) are turned on. At this time, the time constant is the resistance value of the resistor (21) and the time constant of the capacitor (22). It is determined by the capacity, the resistance of the resistor (21) is made small, and the time constant at the time of charging is made small. That is, the charging operation is set so as to quickly follow the change of the caption data. The resistance (23)
And the capacitor (22) is connected to the PMOS transistor (1).
8) A discharge path is formed when (19) is turned off. At this time, the time constant is determined by the resistance of the resistor (23) and the capacitance of the capacitor (22). The time constant at the time of discharge is increased by increasing the value. That is, even if the caption data changes, the capacitor (2
2) The change in terminal voltage, that is, the change in peak value, is minimized. (24) is a voltage follower type operational amplifier, and the + terminal is a resistor (21) and a capacitor (2).
The terminal is connected to the connection point of 2), the output is fed back and the output is connected to the terminal of the comparator (16). The terminal voltage of the capacitor (22) appears at the output of the operational amplifier (24) as it is. In other words, the peak value of the caption data appears. The above is one embodiment of the peak hold circuit of the present application.

The reason why the resistor (20) is provided is as follows. That is, when the terminal voltage of the capacitor (20) reaches the peak value of the caption data, both the PMOS transistors (18) and (19) are turned off. At this time,
Even if the PMOS transistor (19) is off, a small amount of leak current tends to flow through the drain-source path. Then, the terminal voltage of the capacitor (22) may be affected and change. Therefore, by providing the resistor (20), the drain and source voltages of the PMOS transistor (19) are the same even when the PMOS transistor (19) is off.
This is because a leak current can be prevented, and the terminal voltage of the capacitor (22) is not affected by the leak current.

The operation of FIG. 1 will be described below with reference to the waveform diagram of FIG. Note that the 16-bit caption data is, for example, “0110010110110100”. It is also assumed that, for example, the transmission gate (9) is opened as an initial state, and an intermediate reference voltage is applied to the + terminal of the comparator (11). First,
When the video signal 21H arrives, the signal LN21 goes high and is applied to one input of the NAND gate (17), and the NAND gate (17) is enabled. Thereafter, when a run-in clock starts to be generated and is applied to the + terminal of the comparator (16), the charge time constant of the peak hold circuit is small and the discharge time constant is large, as shown by the broken line in FIG. In addition, the terminal voltage of the capacitor (22) rises every time each cycle of the run-in clock occurs. Thereafter, when a start bit “001” is generated, and subsequently 16-bit caption data is generated, during the period in which the caption data is generated, the terminal voltage of the capacitor (22), that is, the output of the operational amplifier (24) becomes the caption. When the high level of the data is almost held, that is, when the caption data changes between the high level and the low level in the normal state, the high level (peak value) is almost held. Since the output of the operational amplifier (24) is applied as a reference voltage to the + terminal of the comparator (11), the caption data can be accurately extracted as information of "1" or "0" in normal times.

If the amplitude of the caption data of 21H is reduced for some reason, the output of the operational amplifier (24) also decreases with the discharge of the capacitor (22). The reference voltage applied to the terminal also drops linearly following the output drop of the operational amplifier (24). From this, the comparator (11)
In, the reference voltage applied to the + terminal is always lower than the high level of the caption data applied to the-terminal, and even if the caption data is abnormal in a short time and the amplitude is reduced, the caption is surely obtained. Data can be extracted.

In this embodiment, the reason why the reference gates are switched by providing the transmission gates (8), (9) and (10) is that the low level of the caption data is originally clamped to Vdd / 2. This is to prevent erroneous extraction of caption data when the low level rises to Vdd / 2 or more due to some influence.

[0020]

According to the present invention, in order to generate a reference voltage required for extracting character data superimposed during one specific horizontal scanning period of a video signal, the character data of one of a plurality of resistors is generated at one end of a plurality of resistors. The output of the peak hold circuit that holds the peak value was connected. As a result, even when the character data fluctuates in an abnormal state, the reference voltage is always smaller than the high level of the character data, and there is an advantage that the character data can be reliably extracted from the video signal.

[Brief description of the drawings]

FIG. 1 is a diagram showing a character data slicing circuit according to the present invention.

FIG. 2 is a diagram showing a conventional character data slice circuit.

FIG. 3 is a diagram showing information of 21H.

[Explanation of symbols]

 (4) (5) (6) (7) Resistance (11) (16) Comparator (17) NAND gate (18) (19) PMOS transistor (21) (23) Resistance (22) Capacitor (24) Operational amplifier

Claims (2)

(57) [Claims] A peak hold circuit for holding a peak value of character data superimposed in a specific horizontal scanning period of a video signal whose pedestal level is clamped at a predetermined potential; A plurality of resistors connected in series between the pedestal level of the video signal and the same voltage; one terminal is connected to each connection point of the plurality of resistors and the other terminal is commonly connected; A plurality of switch circuits selectively forming a signal path, and a divided voltage obtained from a connection point of the plurality of resistors via any one of the plurality of switch circuits is supplied to one input as a reference voltage. A comparator to which the video signal is applied and clamped to the other input; and a predetermined data in the character data based on the output of the comparator.
Determining means for determining whether or not there is data, and dividing the voltage dividing point to a reference voltage at which predetermined data can be obtained.
To set the video based on the output of the determination means.
Select one of the plurality of switch circuits from the image signal
And selecting means for forming a signal path by extracting the character data as digital data of “0” or “1” from the video signal. 2. The method according to claim 1, wherein the selecting means includes a plurality of switches.
A register of the number of bits corresponding to the number of selected paths;
And decodes the contents of any one of the plurality of switch circuits.
And a decoder that selects
Characterized by being changed by the judgment output of the judgment means.
3. A character data slicing circuit according to claim 2.