JP3495565B2 - Data slicer circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data slicer circuit incorporated in a video tape recorder capable of reading data even when a predetermined input signal inserted in a television broadcast signal is distorted. Furthermore, for example, VPS (Video Programming System)
/ VPS / that enables optimization of the slice level of an input signal having a high frequency (for example, 5 MHz to 7 MHz) such as a PDC (program delivery control) signal
The present invention relates to a data slicer circuit for PDC.

[0002]

2. Description of the Related Art A conventional VPS / PDC data slicer circuit will be described. First, from a television broadcast signal having the data slicer circuit built-in, VPS / PDC
The information extraction circuit 1 for extracting data will be described with reference to FIG. The predetermined input signal SV inserted into the television broadcast signal supplied from the input terminal 2 is the information extraction circuit 1
Of the data slicer circuit 4 after the pedestal level is clamped to a predetermined value.
And the sync separation circuit 5.

In the sync separation circuit 5, the horizontal and vertical sync signals are separated from the input signal SV, a gate signal corresponding to the 16th H of the vertical sync interval is formed based on these sync signals, and this gate signal is used as a data slicer. It is supplied to the circuit 4. Then, in the data slicer circuit 4, the VPS inserted in the 16th H of the vertical synchronizing section of the input signal SV.
/ PDC data is extracted.

V extracted by the data slicer circuit 4
The PS / PDC data is supplied to the data decoder 5,
The required data is decoded. This data decoder 5
Data decoded by (national code, broadcasting station code,
The program start date code, etc.) is temporarily stored in the data register 6 and supplied to the channel selection circuit 7 as needed. Incidentally, such a conventional technique is disclosed in JP-A-6-6701.

Then, the data slicer circuit 4 described above is used.
Had the following configuration. That is, the data slicer circuit 4 has an upper limit peak value detection circuit 10 (H peak circuit) for detecting the upper limit peak value (H peak value) of the input signal SV as shown in FIG. The slice level was determined by the upper limit peak value of the input signal SV detected by 10 and the resistance voltage division of 1/2 VDD (VDD is the power supply voltage), and the data was read.

FIG. 6 is a circuit diagram of the data slicer circuit 4. One of the input signals SV is applied to the (+) terminal of the comparator 11 via the node N1, and the other is (+) of the comparator 12. ) Is applied to the terminals,
The output of the comparator 12 is a 3-input NAND circuit 15,
One end (for example, the drain side) is supplied to the gate of a P-channel MOS transistor 18 connected to VDD through the inverters 16 and 17, and the other end (for example, the source side) of the P-channel MOS transistor 18 is a resistor. R3
It is connected to the node N2 via. Also, the node N
One end of the capacitor C1 is connected to 2.

Further, the node N2 is connected to the node N3, and one end of the node N3 has the (+) of the operational amplifier 20.
It is connected to the terminal and the other end is connected to one end of the resistor R4. The output of the operational amplifier 20 is the operational amplifier 20.
Is connected to the (-) terminal of
2 is connected to the (-) terminal. Further, the output of the operational amplifier 20 is connected to one end of the resistor R1 of the resistors R1 and R2 connected in series, and one end of the resistor R2 is 1/2 VDD together with the other end of the resistor R4 and the other end of C1. It is connected to the output side of an operational amplifier 21 which will be described later.

Further, the power supply voltage (VDD) and the ground voltage (VS
A predetermined voltage (1/2 VDD) divided by resistors R5 and R6 connected in series between S) is connected to the (+) terminal of the operational amplifier 21 via a node N4. Further, the output of the comparator 11 is output (Vout) via the 3-input NAND circuit 22 and the inverter 23.

As described above, in the conventional data slicer circuit 4, the upper limit peak value detection circuit 10 detects the upper limit peak value of the input signal SV (see FIG. 7), and the upper limit peak value and 1/2 VDD From the input signal SV input to the (+) terminal of the comparator 11 and the slice level input to the (-) terminal of the comparator 11 to determine data. I was reading.

[0010]

However, when the input signal SV is distorted, particularly when the lower limit peak value of the input signal SV is higher than 1/2 VDD (approximately 2.5 V) described above (see FIG. 8). However, there is a problem in that proper slice data cannot be read because the slice level deviates from the determined slice level.

Therefore, it is an object of the present invention to provide a data slicer circuit capable of reading data even when an input signal is distorted.

[0012]

Therefore, the data slicer circuit of the present invention detects an upper limit value detection circuit for detecting an upper limit value of a predetermined input signal inserted in a broadcast signal, and a lower limit value of the input signal. And a lower limit value detection circuit having a function of following changes in the upper limit value detection circuit, and a reset circuit that resets the upper limit value and the lower limit value for each data, and sets both to a predetermined voltage, The slice level is determined from the upper limit value and the lower limit value detected by the upper limit value and lower limit value detection circuit.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a data slicer circuit of the present invention will be described below with reference to FIGS. First, as shown in FIG. 1, in the data slicer circuit 30 according to the embodiment of the present invention, one of the input signals SV is applied to the (+) terminal of the comparator 11, and the other one is an upper limit peak value detection circuit (H peak circuit). ) 10 and the lower limit peak value detection circuit (L peak circuit) 33.

Subsequently, the upper limit peak value detected by the upper limit peak value detecting circuit 10 and the lower limit peak value detected by the lower limit peak value detecting circuit 33 are connected in series to resistors R1 (about 10 KΩ) and R2 (about 10 KΩ). The slice level obtained by resistance division by 10 KΩ) is output and supplied to the (−) terminal of the comparator 11. Then, the comparator 11 compares the input signal SV with the slice level and outputs the result.

Further, the data slicer circuit 30 resets the upper limit and lower limit peak value data detected by the upper limit peak value detection circuit 10 and the lower limit peak value detection circuit 33 at least every one time of the input signal SV. A reset circuit 34 for resetting is provided. FIG. 2 is a configuration circuit diagram of the data slicer circuit 30 of the present invention. The difference from the conventional data slicer circuit 4 is that the lower limit peak value detection circuit 33 is added to the conventional upper limit peak value detection circuit 10 as described above. In addition, the lower limit peak value detection circuit 33 has a circuit configuration equivalent to that of the upper limit peak value detection circuit 10.

That is, one of the input signals SV is connected to the (+) terminal of the comparator 11 via the node N1,
The other is an upper limit peak value detection circuit (H
The peak circuit 10 is connected to the (+) terminal of the comparator 12 and the lower limit peak value detection circuit (L peak circuit) 33 is connected to the (−) terminal of the comparator 42.

The output of the comparator 42 is supplied via a 3-input NAND circuit 45 and an inverter 46 to the gate of a P-channel type MOS transistor 48 whose one end (for example, the source side) is connected to the ground voltage VSS,
The other end (for example, the drain side) of the P-channel MOS transistor 48 is connected to the node N6 via a resistor R7 (about 65 KΩ). Further, one end of the capacitor C2 (about 20 pF) is connected to the node N6.

Further, the node N6 is connected to the node N7, and one end of the node N7 has (+) of the operational amplifier 50.
The other end is connected to one end of a resistor R8 (about 8 MΩ). The output of the operational amplifier 50 is connected to the (−) terminal of the operational amplifier 50 and the (+) terminal of the comparator 42. Further, the output of the operational amplifier 50 on the lower limit peak value detection circuit 33 side is the resistance R2 of the resistors R1 and R2 connected in series.
The output of the operational amplifier 20 on the side of the upper limit peak value detection circuit 10 is connected to one end of the resistor R1.

The upper limit peak value detection circuit 10 and the lower limit peak value detection circuit 33 are connected to the node 8 located between the resistor R4 (about 12 MΩ) on the upper limit peak value detection circuit 10 side and the operational amplifier 20. By being connected to the node N9 located between the resistor R8 on the lower limit peak value detection circuit 33 side and the operational amplifier 50 via the first and second timing gates (switch circuits) 51 and 52, the lower limit peak value detection circuit Reference numeral 33 is for following changes in the upper limit peak value detection circuit 10.

Further, the power supply voltage (VDD) and the ground voltage (VS
Resistors R5 (about 10 KΩ) and R6 connected in series between S)
Predetermined voltage (1/2 of resistance divided by about 10 KΩ)
VDD) is connected to the (+) terminal of the operational amplifier 21 via the node N4, the output of the operational amplifier 21 is connected to the (-) terminal of the operational amplifier 21, and the resistance R4
And the other end of C1 (about 20 pF).

The output of the comparator 11 is 3
It is output (Vout) via the input NAND circuit 22 and the inverter 23. In this way, the upper limit peak value detected by the upper limit peak value detection circuit 10 and the lower limit peak value detected by the lower limit peak value detection circuit 33 are resistance-divided to determine the slice level. The input signal SV input to the (+) terminal of the comparator 11
And the data is read from the slice level input to the (−) terminal of the comparator 11.

As described above, in the data slicer circuit 30 of the present invention, the upper limit peak value detection circuit 10 detects the upper limit peak value of the input signal SV, and the lower limit peak value detection circuit 33 detects the input signal SV. Of the input signal SV, which has been a problem in the prior art, is detected by detecting the lower limit peak value of (see FIG. 3) and determining the slice level from the upper limit peak value and the lower limit peak value (shown by the dotted line in FIG. 3). Even when the distortion is distorted, for example, when the lower limit peak value is higher than 1/2 VDD, the lower limit peak value is temporarily increased by following the upper limit peak value as shown in FIG. Can be detected.

The reset circuit 34, which is the second feature of the present invention, will be described below. The reset circuit 34 resets the upper limit peak value and the lower limit peak value to 1/2 VDD for each data of the input signal SV as described above, and the slice level determining operation described above is performed by the operation of the reset circuit 34. Is possible. The reset circuit 34
½ VDD, which is resistance-divided by R5 and R6 connected in series between the power supply voltage VDD and the ground voltage VSS, is input to the operational amplifier 21, and the first node N10 located on the output side of the operational amplifier 21 is It is connected to the node N8 via the timing gate 51, and is also connected to the node N9 from the node N10 via the second timing gate 52.

The control signal CS supplied from the sync separation circuit 5 is applied to the first and second timing gates 51 and 5
2 and the timing gates 51 and 52 are closed when the control signal CS is received.
The upper limit peak value and the lower limit peak value are forced to be 1/2 V
Reset to DD (see position A in Figure 3). As described above, in the present invention, the upper limit peak value detection circuit 10 detects the upper limit peak value of the input signal SV, and the lower limit peak value detection circuit 33 detects the lower limit peak value of the input signal SV. By determining the slice level from the upper limit peak value and the lower limit peak value, when the input signal SV, which has been a problem in the past, is distorted, for example, even when the lower limit peak value is higher than 1/2 VDD, Figure 3
As the lower limit peak value following the upper limit peak value once rises as shown at position B, the lower limit peak value can be reliably detected.

Further, according to the present invention, the same slice level determination operation can be performed for each data by the function of the reset circuit 34 that resets the upper limit peak value and the lower limit peak value to 1/2 VDD for each data of the input signal SV. Becomes

[0026]

As described above, according to the present invention, the upper limit value detection circuit detects the upper limit peak value of the input signal, and the lower limit value detection circuit detects the lower limit peak value of the input signal.
By determining the slice level from the upper limit peak value and the lower limit peak value, even if the input signal, which has been a problem in the past, is distorted, for example, even if the lower limit peak value is higher than 1/2 VDD, the upper limit peak value is increased. Since the lower limit peak value following the value once rises, the lower limit peak value can be reliably detected.

Further, by acting as a reset circuit and resetting the upper limit peak value and the lower limit peak value to 1/2 VDD for each data of the input signal, the same slice level determination operation can be performed for each data. Becomes

[Brief description of drawings]

FIG. 1 is a block diagram showing a data slicer circuit according to a first embodiment of this invention.

FIG. 2 is a configuration circuit diagram showing a data slicer circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing characteristics of the data slicer circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional information extraction circuit.

FIG. 5 is a block diagram showing a conventional data slicer circuit.

FIG. 6 is a configuration circuit diagram showing a conventional data slicer circuit.

FIG. 7 is a diagram showing characteristics of a conventional data slicer circuit during normal input.

FIG. 8 is a diagram showing characteristics when an input of a conventional data slicer circuit is distorted.

[Explanation of symbols]

10 Upper limit peak value detector 11 comparator 30 data slicer circuit 33 Lower limit peak value detection circuit 34 Reset circuit SV input signal R1, R2 resistance

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 5/76-5/956 H04N 5/14-5/217 H04N 7/08

Claims (3)

(57) [Claims] 1. An upper limit value detection circuit for detecting an upper limit value of a predetermined input signal inserted in a broadcast signal, and a function of detecting a lower limit value of the input signal and following changes in the upper limit value detection circuit. A lower limit value detection circuit having the data slicer circuit. 2. An upper limit value detection circuit for detecting an upper limit value of a predetermined input signal inserted in a broadcast signal, and a function of detecting a lower limit value of the input signal and following changes in the upper limit value detection circuit. A data slicer circuit, comprising: a lower limit value detection circuit having; and a slice level determined by resistance-dividing the upper limit value and the lower limit value. 3. The data slicer circuit according to claim 1, further comprising a reset circuit that resets the upper limit value and the lower limit value for each data of the input signal and sets both to a predetermined voltage. .