JP3547524B2 - Current clamp circuit - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates generally to a clamp circuit for clamping a signal to a predetermined reference level, and more particularly to a clamp circuit for clamping a signal to a predetermined current level.
[0002]
[Prior art]
In the field of television, it is often necessary to clamp the peak value fluctuation of a television signal, that is, the synchronization signal peak value, to a reference voltage value called a “sync signal peak value clamp level”. By keeping the variation of the television signal within a range of known voltage values, over- or under-modulation of the radio frequency carrier is prevented.
A conventional clamp circuit is described in U.S. Pat. No. 4,914,324 to Goto and is shown as clamp circuit 10 in FIG. 1A of the present application. Clamp circuit 10 includes differential amplifiers 15 and 20 connected together in a loop. The path connecting these amplifiers 15 and 20 is completed by the FET switch 25. The storage capacitor 30 is inserted between one side of the FET switch 25 and the ground point. An input voltage signal V _SIGNAL is provided to the non-inverting input of amplifier 15 and an output signal V _OUT is derived from the output of the amplifier. A voltage reference signal V _{REF is provided} to the inverting input of amplifier 20. The clamp circuit 10 clamps the input voltage V _SIGNAL to the voltage V _REF of the voltage reference signal and acts to produce a clamp output voltage V _OUT .
[0003]
The operation of the clamp circuit 10 will now be briefly described with reference to the graph of the output voltage _VOUT vs. time TIME shown in FIG. 1B. When the FET switch 25 is turned on at the time T1, the voltage of the difference between the output voltage _VOUT and the reference voltage _VREF is fed back to the inverting input of the differential amplifier 15. This difference voltage is applied to the inverting input of the differential amplifier 15 to correct the output voltage level _VOUT . In this way, the output voltage V _OUT is clamped to one particular voltage, which in this example is equal to the reference voltage V _REF . The output of the differential amplifier 20 is held in the holding or smoothing capacitor 30 for holding the clamp state.
[0004]
FIG. 2 shows the video signal 50 both before and after clamping to the reference voltage V _REF . More specifically, video signal 50 includes unclamped video line 55 and video line 60 clamped to voltage V _REF . As seen in FIG. 2, the sync signal peak value 65 of the video line 55 is lower than the reference value, indicating that the video line 55 is unclamped. In contrast, the sync signal peak 70 of the video line 60 has a value equal to the reference voltage V _REF , indicating that the video line 60 is clamped. Clamping of the sync signal peak value to a reference voltage is often used with consumer television products such as video camcorders, but commercial television products often clamp the back porch area of a video signal to a voltage reference signal. .
[0005]
Conventional clamp circuits generally treat signals as voltages and use capacitors and diodes for operation. Such a conventional clamp circuit configuration is shown in FIG. The clamp circuit 100 regenerates an AC coupled signal, that is, a DC component of the capacitor coupling signal. Clamp circuit 100 includes an input capacitor C that couples an input signal to diode D. Many practical clamping circuits use amplifiers to form a super diode configuration. Clamp circuits often include a switch between the diode and ground to gate the clamping operation.
Although clamp circuits that respond to voltage signals are well known, in some applications it may be desirable to have a clamp circuit that is current responsive rather than voltage responsive.
[0006]
[Problems to be solved by the invention]
Accordingly, one object of the present invention is to provide a clamp circuit that operates with current.
It is another object of the present invention to provide a clamp circuit that can clamp to a predetermined reference current level.
Still another object of the present invention is to provide a clamp circuit that can operate at a relatively low operating voltage.
[0007]
[Means for Solving the Problems]
According to one embodiment of the present invention, a current clamping circuit including a current signal input receiving an input current signal is obtained. The current clamp circuit also has a reference current input for receiving a reference current signal. The current clamp circuit further includes a current generation circuit coupled to the current signal input and the reference current input for measuring a current difference between the input current signal and the reference current signal. The current difference generating circuit has an output for generating a current difference between the input current signal and the reference current signal. The current clamp circuit also includes an summing node coupled to the output of the current difference generating circuit for adding the current difference to the input current signal so as to clamp an input current signal to a reference current signal.
[0008]
【Example】
FIG. 4 shows a clamp circuit 200 according to one embodiment of the present invention. Clamp circuit 200 is a current mode clamp circuit as opposed to a well-known voltage mode clamp circuit.
The unclamped current input signal I _SIG is supplied to the clamp circuit 200. It is required that this current signal I _SIG be clamped to the reference current level provided as the I _REF signal. For simplicity, the reference current I _REF is shown by the current source 105 and the unclamped current signal I _SIG is shown by the current source 110. One terminal of the current source 105 and one terminal of the current source 110 are connected to a ground potential point or a negative voltage point, respectively. Another terminal of the current source 105 is connected to a non-inverting input of the current difference generating circuit 115 via a switch 120. If a transconductance amplifier that outputs the difference between two input voltage signals is connected as described here, it can be used as the current difference generating circuit 115. Another terminal of the current source 110 is connected to an inverting input of the current difference generating circuit 115 via a switch 125.
[0009]
Switches 120 and 125 open and close according to clamp pulse clock signal CLPP. The clamp pulse clock signal CLPP is shown in FIG. 5A. In this embodiment, switches 120 and 125 are open (off) when CLPP is low. When CLPP is high, switches 120 and 125 are closed (on). That is, the off / on operation of the switch 120 is performed in cooperation with the on / off operation of the switch 120 according to the CLPP.
A feedback circuit is formed between the output of the current difference generating circuit 115 and the node 130 between the current source 110 and the switch 125. A switch 135 is inserted in this feedback circuit. The complement of CLPP, the inverted output inverted CLPP, is added to switch 135 to control this switch. Thus, when switches 120 and 125 are closed to enable sampling of the I _REF and I _SIG signals, respectively, switch 135 is open, leaving the feedback loop open. Conversely, when switches 120 and 125 are open and the sampling is momentarily stopped between CLPP pulses, switch 135 is closed to form a feedback path. Clock pulse generator 137 generates clamp clock signal CLPP and inverted CLPP.
[0010]
In order to clamp the current signal I _SIG to the reference current level I _REF , the difference between these two current levels is sampled by the current difference generation circuit 115 during the first period T1, as shown in FIG. 5A. The resulting current difference is output by circuit 115 over hold time T2, ie, until the next CLPP as shown in FIGS. 5A and 5B. The current difference between the determined by inverting CLPP The holding time T2 is added to the current signal _{I SIG,} changes its signal level _{I SIG} to clamp the _{I SIG} current signal level to the reference current level _{I REF.} As a result, a clamped signal I _CLAMP is generated at node 130, which is the point of addition of the input current signal I _SIG and the current difference from the output of current difference generation circuit 115. The difference current signal is subtracted or from the signal _{I SIG} is added to the input current signal _{I SIG,} causing clamp output signal _{I CLAMP} to the node 130.
[0011]
FIG. 6 shows a clamp circuit 300 of a more detailed working example of the clamp circuit of the present invention. In the clamp circuit 300 of FIG. 6, the same components as those of the clamp circuit 200 of FIG. 4 are denoted by the same reference numerals. The clamp circuit 300 uses a transconductance amplifier 305 as a current difference generator circuit for determining the difference between these currents receives signals _{I REF} and _{I SIG} to the current input terminal _{I P} and _{I M.} An example of this transconductance amplifier 305 is shown schematically in FIG. 7A. Other transconductance amplifiers can be used as amplifier 305. Amplifier 305 comprises P-channel FETs 311, 312, 313 and 314 and N-channel FETs 315, 316, 317 and 318 connected together as shown in FIG. 7A. The sources of FETs 311, 312, 313 and 314 are connected to a positive voltage source. The gates of the FETs 311 and 312 are commonly connected, and the gates of the FETs 313 and 314 are commonly connected. The drains of FETs 312 and 313 connect to the gates of FETs 312 and 313, respectively, and further connect to the drains of FETs 315 and 316, respectively. Connection point between the drain of the drain and FET315 of FET312 constitutes a current input _{I M.} Connection point between the drain of the drain and FET316 of FET313 constitutes a current input _{I P.} The gate of the FET316 is the voltage input _{V P} of the amplifier 305. Current source of the current, labeled as I _BIAS 320 is inserted between the connection point and the negative voltage supply source of the FET315 and 316. A typical value for the current _IBIAS is 50 μA, but this value can vary from 20 μA to 200 μA.
[0012]
The sources of FETs 317 and 318 are connected to a negative voltage source, and the gates of the FETs are connected in common. The drains of FETs 317 and 318 connect to FETs 311 and 314, respectively. The drain and gate of FET 317 are connected together as shown. The drain and gate of the FET 318 are also commonly connected. A simpler representation of the transconductance amplifier 305 is shown in FIG. 7B.
Referring again to FIG. 6, the reference current signal _{I REF} and the current signal _{I SIG} is supplied through the switch 120 and 125 to the input _{I P} and _{I M} of the transconductance amplifier 305. Outputs _{I O} of the amplifier 305 is fed back to the _{V M} input through the switch 325. The clamp pulse clock signal CLPP is provided to switches 120, 125 and 325, which are open when CLPP is low and closed when high. _{V M} input of amplifier 305 is coupled to a negative voltage source through the storage capacitor 330. _{V P} input of amplifier 305 is coupled to a positive voltage source _{V BIAS.} Voltage _{V BIAS} is set to a nominal value of _{V M} appearing at the inverting input of the transconductance amplifier 305. Change in the output current [Delta] I _O alters the _{V M} from the normal value of _{V BIAS} according to the equation _{ΔV M = ΔI O / g m} . Here, g _m is the transconductance of the amplifier 305. The nominal value of V _M is approximately intermediate value, that is, for example 3 volt system voltage a positive voltage source negative voltage source of 1.5 volts.
[0013]
Output current _IO of transconductance amplifier 305 is added at node 345 to current I _SIG ′ of current source 335. That is, the output of the amplifier 305 is connected to the current source 335 by the switch 340. The I _SIG 'current source 335 is a current source that tracks the I _SIG current source 110. Using for example a current mirror image circuit forming the current sources 335 and _{110, I SIG} 'changes in equally _{I SIG} and _{I SIG} is _{I SIG'} can be made to be reflected as a mirror image to the change of. The inverted CLPP signal shown in FIG. 5B is applied to switch 340 to control the switch operation of switch 340. When the CLPP signal is low, switch 340 is open and the I _REF and I _SIG current signals are sampled by transconductance amplifier 305. However, when CLPP is high, switch 340 is closed and the output of amplifier 305 is provided to current source 335. That is, when the inverted CLPP is high the output current _{I O} which represents the difference between _{I P} and _{I M} is summed with current _{I SIG} 'at node 345. Thus, the current signal at node 345 is clamped to the I _REF signal.
[0014]
The operation of the clamp circuit 300 will now be described in more detail. The transconductance amplifier 305 produces the difference between the I _REF and I _SIG signals during the high period of the CLPP signal of FIG. 5A. The I _SIG signal and the I _REF signal are effectively sampled during the period T 1, and the difference current signal I _O between these signals is determined by the amplifier 305. A holding capacitor 330 assists in the regeneration of the difference current signal over a period T2 between CLPP pulses. That is, the difference current is effectively stored in the battery 330 acting as a storage device. Current is accumulated as _g ^{m *} V. That is, the capacitor 330 stores a voltage that is a function of the transconductance of the amplifier 305 that outputs the current difference.
[0015]
Inverting CLPP waveform of FIG. 5B hold period T2, sets the period T2 which Sunawa value [Delta] V _M is applied to the _{V M} input. Capacitance of capacitor 330 is chosen sufficiently large value so as not to value [Delta] V _M that is fed back to the V _M input during the holding period T2 undergo significant degradation due to leakage currents. For example, in one embodiment of the invention, a capacitance value C _HOLD of about 15 pF is sufficient. A typical value for the width T1 of the CLPP pulse is 2 μs, which corresponds to half the video sync peak period. A typical value of the width T2 of the inverted CLPP pulse is 64 μs, which corresponds to one horizontal scanning period. Note that the above numbers are for specific applications and are for illustration. These numbers should not be construed as limiting. The actual values for this clamp circuit will depend on the particular application. During the closed hold period T2 of switch 340, the difference current at the output of amplifier 305 is added at node 345 to current I _SIG '. In this way, the DC current level of the input current signal _ISIG is corrected for realizing the clamping action.
[0016]
Note that amplifier 305 has a connection that receives a bias voltage V _BIAS at its non-inverting input terminal. The feedback circuit is formed between the output of the amplifier 305 and the inverting input terminal. The voltage at the inverting input terminal of amplifier 305 is maintained at a value such that current does not flow in or out of amplifier 305 through this terminal.
When the input current _{I P} and _{I M} are removed by the switches 120 and 125 are opened, because the _V P -V _M is accumulated in the holding circuit 330, the output current _{(I O)} of the amplifier 305 _{I M} minus I to become _{P (I O = I M -I} P). This output current _IO is a difference current, that is, a difference current that is added to the signal current I _SIG ′ at the node 345 during the holding period T2 in which the switch 340 is open.
[0017]
Another embodiment of the present invention uses a MOSFET or bipolar super-mirror circuit to minimize base current errors in the clamp circuit. The super mirror image circuit is used, for example, in the current source I _SIG . In addition, the transconductance circuit 305 can use cascaded devices to increase the output impedance and thereby increase the current accuracy.
In the clamp circuit 350 of another embodiment shown in FIG. 8, capacitors 330 and 335 and switches 325 and 360 having the same characteristics are used for the voltage input of the transconductance amplifier 305 to minimize the charge injection and delay in the CLPP pulse. I have. Switches 380 and 385 direct the current from amplifier 305 to the power supply circuit rather than to open the current mirror circuit when the current mirror circuit is used as current sources 110 and 335. Switches 325 and 360 open and close at the same time. When these switches are open, the charge injection at the inverting input of the amplifier 305 matches at the non-inverting input of the amplifier, resulting in a common mode signal that the amplifier can block.
[0018]
FIG. 9 shows a clamp circuit 400 according to another embodiment of the present invention. Clamp circuit 400 includes an input current source 110 representing an input current signal I _SIG to be clamped to a reference current level I _REF . Clamp circuit 400 also includes a reference current source 105 that produces an output current at a desired reference current level I _REF . The current difference generating circuit 420 such as a transconductance amplifier is arranged in the clamp circuit 400 as shown in FIG.
The current difference generating circuit 420 includes P-channel MOSFETs 421, 422, 423 and 424 and N-channel FETs 431, 432, 433 and 434 connected to each other as shown in FIG. The sources of P-channel MOSFETs 421, 422, 423 and 424 are connected to a positive voltage source. The sources of N-channel FETs 433 and 434 are connected to a negative voltage source. The sources of N-channel FETs 431 and 432 are connected to a negative voltage source via current source 442. Drain of FET421 and 431 is connected to a current source 110 through the switch 440 connected in common, so that _{I SIG} is supplied to the current difference generator 420 under the control of CLPP signal. The gate and drain of FET 422 are commonly connected to the gate of FET 423. The current source 105 is connected to the connection point between the drain of the FET 422 and the drain of the FET 432 via the switch 425 so that the supply of the reference current I _REF is controlled under the control of the CLPP signal.
[0019]
The gate and drain of the FET 421 are commonly connected to the gate of the FET 424. The gate and drain of FET 420 are commonly connected to the gate of FET 423. The gate of FET 432 is connected via switch 445 to the junction of the drain of FET 424 and the drain of FET 434. The holding capacitor 450 is inserted between the gate of the FET 432 and the negative voltage source. The output signal of amplifier 420 appears at an output 420A formed at the junction of the drains of FETs 424 and 434. The difference between currents I _REF and I _SIG appears at output 420A as a current difference signal. This current difference signal is supplied to the addition node 455 via the switch 460 between the output 420A and the addition node 455. The current signal I _SIG ′ of the current source 465 is also applied to the summing node 455 to generate a clamp signal from the sum of the current difference signal and the current signal I _SIG ′.
[0020]
The inverted CLPP signal is supplied to a switch 460 which is open during the T1 period of CLPP and closed during the T2 period. In this way, the I _REF and I _SIG signals are effectively sampled during the high period (T1) of CLPP to determine the current difference signal, and the current difference signal is used during the holding period T2 for the original signal I _SIG. With the mirror image signal I _SIG ′. The holding capacitor 450 holds a relatively constant difference current signal during the period T2 when CLPP is high. Output current signal I _CLAMP is thus obtained at summing node 455 clamped to current level I _REF .
[0021]
That is, the current difference I _REF -I _SIG is effectively sampled during the high period of the CLPP pulse of FIG. 5A. In FIG. 9, it can be seen that a feedback loop from the output 420A is formed. Because the feedback loop from output 420A is closed, the gain of amplifier 420 pulls the voltage at output 420A (V _A ) to a value approximately equal to V _REF (ie, V _A ≒ V _REF ). This condition occurs when the change ΔI _BIAS of the bias current I _BIAS via the FET 421 is equal to the difference between the currents I _REF and I _SIG (ie, when ΔI _BIAS = I _REF −I _SIG ). The required bias level of the FET 432 is held in the holding capacitor 450 during the holding period T2 of the inverted CLPP pulse. This required bias level is the difference from V _REF required to set the current to ΔI _BIAS determined by the formula ΔI _BIAS = g _m ^* bias level. Where g _m is the transconductance of amplifier 420. In the clamp circuit 400, the normal value of _IBIAS is 50 μA. The normal value of the capacitor 450 is 15 pF, and the normal values of I _SIG and I _REF are both 50 μA.
[0022]
During the holding period T2, the input currents I _SIG and I _REF are not supplied to the amplifier 420. Thus, a net current difference equal to I _REF minus I _SIG occurs at output 420A. This current difference is summed with current I _SIG ′ at summing node 455, producing an output clamped to current level I _REF .
Although the current clamp circuit device has been described above, the method of the current clamp has also been described. Briefly, a method has been described for clamping an input current signal to a reference current value, i.e., a method for generating a clock signal representing first and second logic levels. The method includes providing an input current signal and a reference current signal to a current difference generation circuit during the first logic level of a clock pulse. The method further includes determining, by the current difference generating circuit, a current difference between an input current signal and a reference current signal during the first logic level of the clock pulse. The method also includes accumulating the current difference obtained from the determining step and providing a current difference accumulation value. Further, the method includes adding the accumulated current difference to the input current signal during the second logic level of the clock pulse to clamp the input current signal to a reference current value.
A current clamp circuit that operates on a current signal rather than a voltage signal has been described above. The current clamp circuit clamps an input current signal to a predetermined reference current level at a relatively low operating voltage such that the potential difference between the positive and negative voltage sources is, for example, 3 volts.
[0023]
【The invention's effect】
As described above, according to the present invention, a low power supply voltage operation current clamp circuit that clamps an input current to a predetermined reference current level can be obtained.
While some preferred features of the invention have been illustrated above by way of example, many variations and modifications are possible. Accordingly, each of the claims is intended to cover all such variations and modifications that fall within the scope of the invention.
[Brief description of the drawings]
FIGS. 1A and 1B are a block diagram of a conventional clamp circuit and a graph of a change in voltage versus time showing a clamping action of the clamp circuit.
FIG. 2 is a graph showing a change over time of a voltage indicating a video signal including an unclamped line and a clamped line.
FIG. 3 is a block diagram of another conventional clamp circuit.
FIG. 4 is a simplified block diagram of a clamp circuit according to the embodiment of the present invention.
5A is a diagram illustrating a change in voltage of a clamp pulse clock signal (CLPP) with respect to time for driving the clamp circuit of FIG. 4;
FIG. 5B is a diagram illustrating a change in voltage of a complement (inverted CLPP) of the clamp pulse clock signal for driving the clamp circuit of FIG. 4 versus time.
FIG. 6 is a circuit diagram of a more detailed example of actual operation of the clamp circuit of the present invention.
FIG. 7A is a schematic diagram of a transconductance amplifier that can be used in the clamp circuit of FIG. 6;
(B) is a simplified representation of the transconductance amplifier of FIG. 7A.
8 is a schematic diagram of a clamp circuit modified by adding a capacitor and a switch having the same characteristics to the clamp circuit of FIG. 6;
FIG. 9 is a schematic diagram of a clamp circuit according to another embodiment of the present invention.
[Explanation of symbols]
10, 100 Clamp circuit 15, 20 Differential amplifier 25 FET switch 30, C Holding capacitor 50 Video signal 55, 60 Video line 65, 70 Horizontal synchronization signal peak value D diode 200, 300, 350, 400 Clamp circuit 105 Reference current (I _REF ) source 110 Unclamped input current (I _SIG ) source 120, 125, 135 Switch 115 Current difference generator 130 Summing node 137 Clock pulse generator CLPP Clamp clock signal 305 Transconductance amplifier 311-314 P-channel FET
315-318 N channel FET
320, 442 Bias current (I _BIAS ) source 325, 340, 360 Switch 330, 355, 450 Holding capacitor 335, 465 Current signal (I _SIG ') source 420 Current difference generating circuit 421-424 P-channel MOSFET
431-434 N-channel FET
425, 440, 445, 460 Switch 420A Output 455 Addition node

Claims (7)

Current input terminal IP
And IM and voltage input terminal VP
And VM and output terminal IO
A transconductance amplifier comprising:
A reference current signal source for supplying a reference current signal;
A first input current signal source for providing a first input current signal;
A second input current signal source that mirrors the first input current signal source and provides a second input current signal;
A first switch inserted between the reference current signal source and the current input terminal IP;
The first input current signal source and the current input terminal IM
A second switch inserted between
A clock pulse signal generator connected to the first and second switches for generating a clock pulse signal representing first and second logic levels, wherein the clock pulse signal has a period of the first logic level A clock pulse signal generator that closes the first and second switches and produces a current difference signal at the output terminal IO of the amplifier in response thereto;
The amplifier is connected between the output terminal IO of the amplifier and the second input current signal source, and is connected to the clock signal generator so as to close during the second logic level of the clock pulse signal. A third switch for adding the current difference signal to the second input current signal so that the first input current signal is clamped to the reference current signal. Current clamp circuit of claim 1, further comprising a summing node between the output terminal IO and the third switch of the amplifier. It said third current clamp circuit of claim 1, further comprising a summing node between the switch and the second input current signal source. 2. The current clamp of claim 1 wherein said first and second switches decouple said reference current signal source and said first input current signal source during said second logic level of said clock pulse signal. circuit. And a fourth switch disposed between the output terminal IO of the amplifier and the voltage input terminal VM of the amplifier to form a feedback path between the clock pulse signal and the first logic level during the first logic level. Item 2. The current clamp circuit according to Item 1 . Voltage input terminal VM of the amplifier
6. The current clamp circuit according to claim 5 , further comprising a storage capacitor connected to the input terminal VM for storing the current difference signal fed back to the input terminal VM. Voltage input terminal VP of the amplifier
7. The current clamp circuit of claim 6 , further comprising a voltage bias source connected to the current clamp circuit.

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