JPS61184055A - Synchronous separator circuit of television receiver - Google Patents

Abstract

PURPOSE:To prevent multiple trigger by providing an operational amplifier whose 1st input connects to a capacitor and whose 2nd input receives a bias voltage. CONSTITUTION:A positive composite video signal is fed to an inverting input of the operational amplifier OA via a capacitor C and a voltage dividing a power supply voltage VDB by resistors R1, R2 is fed to a non-inverting input. An output of the operational amplifier OA is outputted to a synchronous separator output terminal 3 via a converters I1, I2 and a phase compensation circuit B. The reason why the operational amplifier is used is to prevent multiple trigger. That is, since the operational amplifier OA incorporates the phase compensation circuit, the relation between the rising speed (tr) of the signal passing through an active region of the amplifier OA and a response speed ts of the amplifier OA is expressed as tr<ts and the multiple trigger hardly takes place and a sharp operation is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization separation circuit used in television receivers.

Conventional technology In recent years, the synchronization separation circuit of television receivers is also C-MOS.
It has become possible to save energy and to use Ls technology.

An example of a synchronous separation circuit of a conventional television receiver will be described below with reference to the drawings.

FIG. 2 shows a synchronous separation circuit of a conventional television receiver.

In FIG. 2, (1) is a power supply line, (2) is a video signal input terminal, (3) is a synchronization separation output terminal, and A is a comparator. is the inverter N Ql is P −M
OSFET, Q5. indicates N-MO3FE'I'.

Q, + and Q2 constitute a 0-MOS inverter.

A voltage obtained by dividing the power supply voltage VDD by resistors R and R2 is applied to the input terminal of the comparator A.
A positive-polarity reverse video signal is applied to the input terminal of The output compared by this comparator A is comparator E.

It is output to the synchronous separation output terminal (3) via the terminal 2.

On the other hand, the output of the inverter is the gate electrode of P-MO3FET Q, 1 and the gate electrode of N-MOSFET Q, 2 (7)
connected to the electrode. The source electrodes of the P-MO8FETQ,1 are connected to the power supply line (1) via a resistor R3, and the source electrodes of the N-MO3FETQ,2 are grounded via a resistor R1. P-MO3PETQ, and N-MO
3F] The connection point of the drain electrode of IcTQ, 2 is connected to the input terminal of comparator A (to).

The operation of the synchronization separation circuit of the television receiver configured as described above will be explained below.

FIG. 3.4 shows voltage waveforms at various parts in the circuit configuration of FIG. 2. In Figure 3, (4) is the (
The input terminal voltage of (5) is a voltage waveform at the input terminal of comparator A, to which a positive polarity composite video signal is applied. The bias voltage (6) of this video signal is such that Q,+ and Q,2 are turned on and off alternately at times T and T2 by the output compared by comparator A, and capacitor C1
This is the average value of the battery aE(7) charged and discharged. This charging/discharging voltage (7) is Q during the horizontal synchronizing signal period T, = 5 μsec.
5. is turned on and charged with the time constant of c and R3, and the scanning period T
2 = 58.5 usec, Q and 2 turn off, and C and R4
This is the voltage discharged with a time constant of . R4/R3=T2/T
.

If set to , the bias voltage (6) will be approximately vDD/2, but here R4/R3 is set to T2/T, = 11.
7, and the bias voltage (6) is set so that the synchronous part of the video signal becomes VDD/2. The input video signal increases and the pedestal level (8) of the input video signal to the comparator A and the video section reach the level of the input voltage (4) of the comparator A (which becomes the synchronous separation level). Then, the charging time becomes longer than T1, the bias voltage (6) of this video signal becomes high, and the synchronous part of the video signal is set to be VDD/2. Conversely, if the input video signal becomes small or the synchronization part of this video signal becomes small and the charging time becomes 0, the bias voltage (6) of the video signal becomes low, and similarly the video signal The synchronization part is corrected to be VDD/2. In Fig. 4, Qfl is the synchronous separation output terminal (3
) is the voltage waveform.

Problems to be Solved by the Invention However, the above configuration has the following problems. In the input video signal, there is actually noise in the peak and pedestal parts of the synchronization signal, and when the synchronization separation level is close to these levels, the noise will cause comparator A to move, and the synchronization separation output will be An oscillating waveform is output. This is generally referred to as multiple triggers. This multiple trigger makes the range of synchronization separation capability very narrow, which causes problems such as image distortion in the case of top curl or weak electric field.

Means for Solving the Problems The present invention provides an operational amplifier with a capacitor connected to the first input and a bias voltage applied to the second input, and an 0-MOS that is turned on and off alternately by the output of the operational amplifier.
comprising first and second switches configured with
A second switch charges the capacitor with current and connects the phase compensation circuit to the output stage.

Effect of the Invention With the above-described configuration, the present invention eliminates the occurrence of multiple triggers due to the characteristics of the operational amplifier, improves the synchronous separation ability, and provides a stable synchronous separation output.

Embodiment FIG. 1 shows a circuit diagram of an embodiment of a synchronization separation circuit for a television receiver according to the present invention.

B indicates a phase compensation circuit. The reason why the operational amplifier OA is used here is to prevent multiple IJ problems. One of the causes of multiple triggers is the high speed of the comparator, but since the operational amplifier has a built-in phase compensation circuit, the rise speed tr of the signal passing through the active region of the operational amplifier and the response speed ts of the operational amplifier are equal to tr(ts). As a result, multiple triggers are less likely to occur, resulting in clean operation.However, since the speed of an operational amplifier is slow, a phase lag occurs between the input and output waveforms, and the phase compensation required for synchronously separated output is required. In the invention, a phase compensation circuit A is connected to the output end.

As described above, according to the embodiments of the present invention, the adverse effects caused by multiple triggers can be prevented.

Effects of the Invention According to the configuration of the present invention, it is possible to prevent multiple IJ errors due to the characteristics of the operational amplifier, and correct the drawbacks of the operational amplifier using the phase VI circuit, thereby improving the synchronization separation ability and providing stable synchronization separation output. It produces the effect of

[Brief explanation of drawings]

FIG. 1 is a diagram of an embodiment of the synchronous separation circuit of a television receiver according to the present invention, FIG. 2 is a diagram of a synchronous separation circuit of a conventional television receiver, and FIGS. 3 and 4 are diagrams of a conventional television receiver. (The waveform diagram of each part of the synchronous separation circuit of '11 TL is shown. 1: Power supply line 2: Video signal input terminal 3: synchronous separation output terminal C1: Capacitor OA = operational amplifier Q
,, : P-MOS FETQ4 'N MOS
FIcT R+ + R2+ R3+ R4'
Resistance work 1. Engineering 2; Inverter B: Phase compensation circuit patent applicant Patent attorney representing Matsushita Electric Industrial Co., Ltd.
Isao Abe Figure 3, Ward 41

Claims (1)

[Claims] An operational amplifier is provided with a capacitor connected to the first input and a bias voltage applied to the second input, and first and second switches configured with C-MOS are alternately turned on and off by the output of the operational amplifier. A synchronous separation circuit for a television receiver, characterized in that the first and second switches charge and discharge current to the capacitor, and a phase compensation circuit is connected to an output stage.