JPH0991987A - Sample hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a sample hold circuit comprising a switching circuit of diode ring structure employing a pair of complementary sample pulses in which asymmetry of complementary sample pulse is improved and S/N ratio is prevented from deteriorating due to switching noise. SOLUTION: A pair of complementary pulses b, c are inputted to the primary of a pulse transformer 14 through capacitors 12, 13. When the pulse transformer 14 is earthed at the primary neutral thereof, currents induced to flow from the primary input end to the neutral are canceled each other and two pulses are smoothed such that the asymmetric intervals thereof are made symmetric. When a diode ring 17 is turned on/off by the symmetric complementary pulses, switching noise is removed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a diode ring circuit provided so that four bridge-connected diodes are simultaneously turned on and off by a bias voltage between two opposing connection points of the bridge. The present invention relates to the sample hold circuit used.

[0002]

2. Description of the Related Art Charge-coupled devices (CCDs) are becoming more and more pixels in order to achieve high image quality.
Is being developed. As the number of CCD pixels increases, the clock rate of the driving clock pulse of the CCD increases and the area of the photodiode per unit pixel decreases, so that the sensitivity per pixel tends to decrease.

In the signal processing circuit which handles the output signal of the CCD having such a tendency, particularly in the sample hold circuit, it is required to reduce the noise at the same time as the speed.

FIG. 4 shows an example of a conventional sample and hold corresponding to the speedup. In FIG. 4, the analog video signal a (VIDEO IN) to be sampled is input to the diode ring circuit 17 via the buffer 19. The diode ring circuit 17 has a bridge connection configuration of four diodes, and these diodes have a polarity such that they are simultaneously turned on or off by an applied bias between α and β at two opposing connection points of this bridge. It is connected.

The video signal via the buffer 19 is applied to one point δ of the two opposing connection points δ and γ of the diode ring circuit and is derived from the other point γ. A hold capacitor 1 is placed between this point γ and ground.
8 is provided, and the hold output of the hold capacitor 18 is led to the outside as a sample hold output via the buffer 20 and supplied to the signal processing circuit of the next stage.

On the other hand, a clock pulse CLK having a sampling period is input to the differential pulse generator 10, and the differential pulse generator 4 generates a differential pulse having a constant pulse width in synchronization with the clock pulse CLK. The pulse width of this differential pulse determines the sampling width, and its period determines the sampling period.

This differential pulse is generated by the complementary pulse generating circuit 11
Is input to and converted into a pair of positive and negative polarity sample pulses b and c which are complementary to each other. This complementary pulse generation circuit 1
Reference numeral 1 includes two-input exclusive NOR gates 111 and 112. The exclusive NOR gate 111 has a positive power supply Vcc and a differential pulse as two inputs, and the exclusive NOR gate 112 has a ground and a differential pulse as two inputs.

A pair of positive and negative polarity sample pulses b and c are supplied to the two opposing connection points α and β of the diode ring circuit 17 via the diodes 30 and 31, respectively, and the diode ring circuit 17 is turned on and off. It is possible.

The current sources 32 and 33 serve as bias currents for the respective diodes of the diode ring circuit 17.

FIGS. 4 (a) to 4 (d) show examples of waveforms of signals a to d in each part of the circuit of FIG. 3, and partially enlarged waveforms ((b) to (b)).
(D)) is also shown.

When the sample pulse c is at the high level and the sample palace b is at the low level, all the diodes of the diode ring circuit 17 are turned on, so that the diode ring circuit 17 is supplied with current from the current source 32, It is ready to be swept out to source 17. Therefore, the potentials at the input point δ and the output point γ of the diode ring circuit 17 become equal, and the switch is turned on.

Next, when the sample pulse c is at the low level and the sample pulse b is at the high level, the current source 3
Each of the currents 2 and 33 flows through the diodes 31 and 30, and the switch is turned off.

As is apparent from the above operation, the diode ring circuit 17 is turned on to enter the sampling state only when the complementary sample pulses b and c are applied, and is in the hold state in other periods.

[0014]

In the circuit described above,
The symmetry of the pair of complementary pulses b and c is not perfect as shown in the enlarged view of FIG. 5 (see (b) to (d) on the lower side). There is a gap between the timing at which the current is supplied and the timing at which the current is absorbed. As a result, the sample hold output d
As shown in FIG. 5D, the switching noise Nsw appears.

An object of the present invention is to provide a sample hold circuit capable of eliminating switching noise caused by such asymmetry of a pair of complementary pulses b and c.

[0016]

SUMMARY OF THE INVENTION In a sample and hold circuit according to the present invention, four bridge-connected diodes are provided so that they are simultaneously turned on or off by a bias voltage between two opposing connection points of the bridge. The ring circuit and the diode ring circuit described in 2 above.
Sample pulse supplying means for supplying a pair of complementary sample pulses having a predetermined period between the connection points, and a holding capacitor connected to one of the other two opposite connection points of the diode ring, and the other opposite. A sample and hold circuit configured to sample and hold an analog signal supplied from the other of the two connection points by the halt capacitor and output the sample and hold circuit, wherein the sample pulse supply means has a pair of complementary pulses on the primary side. It has a transformer which is applied between the terminals of the transformer and whose midpoint on the primary side is grounded, and the output on the secondary side of this transformer is used as a bias pulse between the two opposing connection points.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The operation of the present invention will be described. In the present invention, in order to eliminate the asymmetry of the pair of complementary sample pulses, the sample pulse is supplied to the primary side of the pulse transformer in which the midpoint of the primary side is grounded. By grounding the midpoint of the primary side of the pulse transformer, it is possible to prevent the asymmetry of the pair of complementary sample pulses applied between the terminals on the primary side due to the self-induction action of the inductor. Improvement is possible.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and the same components as those in FIG. 4 are designated by the same reference numerals. In FIG. 1, a portion different from FIG. 4 will be described. The pair of complementary pulses b and c from the complementary pulse generating circuit 11 are supplied to the primary side terminals of the pulse transformer 14 via the capacitors 12 and 13, respectively.

The midpoint of the primary side of the pulse transformer 14 is grounded, and a damping resistor 15 for preventing ringing is connected between the secondary side outputs of the transformer 14. Then, a pair of complementary sample pulses d and e with greatly improved symmetry are generated from both ends on the secondary side.

This pair of complementary sample pulses d and e
Is a parallel circuit of the resistor 21 and the capacitor 23 and the resistor 2
2 and capacitors 24 are connected in parallel to each other, and are respectively input to the connection points α and β of the diode ring circuit 17 which face each other.

Since the other structure is the same as that of FIG. 4, the description thereof will be omitted.

An example of the differential pulse generator 10 shown in FIG. 1 will be described with reference to FIG. FIG. 2A is a specific example circuit diagram thereof, which is a generally known digital differentiating circuit, and FIG. 2B is a signal waveform diagram of each part of FIG.

Clock pulse CL of sampling period T
K is inverted in NAND gate 101 to become an inverted pulse, which is delayed in delay circuit 102 for time τ. This delay pulse is one input of the NAND gate 103 and is NAND-processed with the clock pulse CLK.

The NAND output is inverted by the inverter 104 and becomes a positive pulse, which is output as a pulse having a sampling width t (output of the differential pulse generator of FIG. 1).

FIGS. 3 (a) to 3 (f) respectively show the waveforms of the signals a to f in the circuit of FIG. 1, and the partially enlarged waveforms ((b) to (f)) are also shown. are doing. Incidentally, a is an analog video input signal, b and c are a pair of complementary pulses, and d and e.
Is a pair of complementary sample pulses, and f is a sample hold output.

Clock pulse CL of sampling period T
In the differential pulse generator 10, K is converted into a pair of complementary pulses b and c in the differential pulse generator 10 as a pulse having the period T and having a sampling width t and input to the complementary pulse generation circuit 11.

At this time, due to the difference in response between the rising characteristics and the falling characteristics of the exclusive NOR gates 111 and 112 in the complementary pulse generating circuit 11, a pair of complementary pulses b,
c does not become a perfect ideal complementary pulse, but becomes an asymmetrical pulse waveform that is shifted in time (see enlarged waveforms (b) and (c) on the lower side of FIG. 3).

However, in the embodiment of the present invention, the pair of complementary pulses b and c are capacitors 12 and 1, respectively.
Since the middle point is applied to the primary side of the pulse transformer grounded via 3, the current flow from the input end of the primary side to the middle point cancels each other due to the electromagnetic induction effect of the primary side inductor. Therefore, the complementary sample pulses d and e which are almost symmetrical on the secondary side are obtained.
Will be generated.

The pair of symmetrical complementary sample pulses d and e are applied to the connection points α and β of the diode ring circuit 17 via the capacitors 23 and 24, respectively. When the sample pulse e is at a high level and the sample pulse d is at a low level, all the diodes in the diode ring circuit 17 are forward biased, and thus are switched on. This state is the sampling state.

On the other hand, when the sample pulse d is at the high level and the sample pulse e is at the low level, all the diodes are reverse-biased and are switched off. This state is the hold state. In this state, the electric charges charged in the capacitors 23 and 24 are discharged by the resistors 21 and 22.

Through the above series of operations, the analog video signal a is sampled and held in the hold capacitor 18 at the frequency of the sample clock. The sampling width t can be selected as desired by the delay time τ of the delay circuit 102 in FIG.

[0033]

As described above, according to the present invention, the asymmetry of the complementary sample pulse can be almost eliminated by the pulse transformer connected to the midpoint of the primary side. The switching noise caused by the imbalance between the current supplied to the diode ring circuit and the current discharged during the transient response is significantly suppressed, and the noise reduction is achieved and the S / N characteristic is improved. .

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

2A is a diagram showing a circuit example of a differential pulse generator of the circuit of FIG. 1, and FIG. 2B is a waveform diagram of each part showing its operation.

FIG. 3 is a signal waveform diagram of each part of the circuit of FIG.

FIG. 4 is a diagram showing an example of a conventional sample hold circuit.

5 is a signal waveform diagram of each part of the circuit of FIG.

[Explanation of symbols]

 11 Complementary pulse generator circuit 12 Differential pulse generator 12, 13, 23, 24 Capacitor 14 Pulse transformer 15, 21, 22 Resistor 17 Diode ring circuit 18 Hold capacitor 19, 20 Buffer

Claims (3)

[Claims] 1. A diode ring circuit provided so that four bridge-connected diodes are turned on or off at the same time by a bias voltage between two opposing connection points of the bridge, and the two diode ring circuits described above.
Sample pulse supplying means for supplying a pair of complementary sample pulses having a predetermined period between the connection points, and a holding capacitor connected to one of the other two opposite connection points of the diode ring, and the other opposite. A sample and hold circuit configured to sample and hold an analog signal supplied from the other of the two connection points by the halt capacitor and output the sample and hold circuit, wherein the sample pulse supply means has a pair of complementary pulses on the primary side. A sample-hold circuit having a transformer which is applied between the terminals of the transformer and whose midpoint on the primary side is grounded, and whose secondary side output is a bias pulse between the two opposing connection points. 2. A damping resistor is connected between the secondary side terminals of the transformer.
Sample hold circuit described. 3. A parallel circuit of a capacitor and a resistor is provided between each terminal on the secondary side of the transformer and the two opposing connection points, respectively. Sample hold circuit described.