JP2514486B2 - Image sensor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image sensor of a type in which a plurality of photodiodes are sequentially scanned based on a sawtooth wave.

[0002]

2. Description of the Related Art A typical conventional image sensor includes a plurality of photodiodes for converting light information into electric signals and a plurality of photodiodes for electrically scanning the plurality of photodiodes to selectively obtain electric signals. And an analog switch. By the way, in this type of image sensor,
The width of one photodiode or one pixel (eg 12
One field-effect transistor-like analog switch must be placed to fit within 5 microns. However, it is not easy to form an analog switch so as to fit in an extremely narrow width. To solve this problem, it is possible to obtain a voltage for sequentially scanning a plurality of photodiodes by applying a sawtooth voltage to a series circuit of a plurality of diodes.
No. 9 publication.

[0003]

However, in the method disclosed herein, the mutual time intervals of scanning of a plurality of photodiodes are not always constant. Therefore, the sampling timing in the sample and hold circuit for extracting the current component of each photodiode from the combined output current of the plurality of photodiodes cannot be set to a constant cycle, and the change in scanning voltage or current of each photodiode is not possible. Is required to be detected by a differentiating circuit or the like to form a sample and hold control signal (sampling pulse), which inevitably complicates the circuit. Also, the forward voltage of the diodes connected in series changes due to temperature changes,
The scanning speed of the photodiode and the sample-hold time change. If the timing of sample and hold changes in this way, it becomes difficult to synchronize with an external circuit.

Therefore, an object of the present invention is to provide an image sensor which can easily and properly obtain a control signal for sampling and holding the output current of a photodiode and can reduce the change in output timing. Especially.

[0005]

The present invention for achieving the above object will be described with reference to the reference numerals of the drawings showing an embodiment. A sawtooth wave generating circuit 4 for periodically generating a sawtooth wave, and an image A sensor circuit block B1, a timing signal forming dummy circuit block B0 having substantially the same configuration as the image sensor circuit block B1, and a first current connected to the image sensor circuit block B1.
A voltage conversion circuit 7, a sample and hold circuit 8 connected to the first current-voltage conversion circuit 7, a second current-voltage conversion circuit 9 connected to the dummy circuit block B0, and the second And a sample and hold control signal forming circuit 10 for forming a sample and hold control signal of the sample and hold circuit 8 based on the output of the current-voltage conversion circuit 9 of FIG.
And the dummy circuit block B0 is a circuit in which a plurality of first diodes Da1 to Da3 each having a first electrode and a second electrode are connected in series, one end of which is the sawtooth wave generating circuit. Is connected to the first diodes Da1 to Da3, and the plurality of first diodes Da1 to Da3 have directivity such that the forward currents of the first diodes Da1 to Da3 flow based on the sawtooth wave. First
From the first resistors Ra1 to Ra3 or the first capacitors C1 to C3, the first series circuits in which the first electrodes of the diodes Da1 to Da3 are arranged on the side of the sawtooth wave generating circuit, respectively. A first impedance element and a second diode Db1 to Db3 or resistors R1 to R3 connected in series, and the second electrodes of the plurality of first diodes Da1 to Da3 and a common power supply terminal ( Ground) and a plurality of the second
Second series circuits in which the plurality of second diodes Db1 to Db3 have a directivity such that the forward currents of the diodes Db1 to Db3 flow based on the sawtooth wave, and the plurality of second series circuits. The second one of the diodes Da1 to Da3 of one
Second impedance element composed of a plurality of second resistors Rb1 to Rb3 or second capacitors Cb1 to Cb3, which are respectively connected between the electrodes of the first power supply terminal and the common power supply terminal (ground), and one end of the first impedance element The dummy circuit block B0 is composed of a plurality of photodiodes S1 to S3 which are respectively connected between an impedance element and the second diodes Db1 to Db3 or resistors R1 to R3, and the other ends of which are commonly connected to each other. The photodiodes S1 to S3 of the image sensor circuit block B1 to B3 are formed so as to have a larger leak current than the photodiodes S1 to S3 of the image sensor circuit block B1 to B3, and the first and second current-voltage conversion circuits 7 , 9 are the image sensor circuit block B
1 and the dummy circuit block B0 are respectively connected between the common connection point of the other ends of the plurality of photodiodes S1 to S3 and the common power supply terminal (ground), and the sample and hold control signal forming circuit 10 is Second
Is configured to form the sample and hold control signal based on an AC component indicating scanning of the photodiodes S1 to S3 obtained from the current-voltage conversion circuit 9 of FIG.
Clock pulse generating means for generating a clock pulse at a constant cycle is provided, and a correction signal is formed by detecting a phase change of the sample and hold control signal based on the clock pulse, and a correction signal is formed by a change in the slope of the sawtooth wave. The present invention relates to an image sensor provided with a correction circuit for controlling the sawtooth wave generation circuit with the correction signal so as to correct the phase change.

It is desirable that a shift register is provided at the output stage of the sample and hold circuit and a clock pulse having a constant cycle is used as a read clock of the shift register. Further, instead of increasing the leak current of the photodiodes S0 to S3 of the dummy circuit block B0, the photodiodes S1 to S of the image sensor circuit block B1 are replaced.
It can be formed in the same manner as 3, and a leak circuit such as a resistor can be connected in parallel to this, or a constant light input can be given.

[0007]

The dummy circuit block B0 in the present invention is constructed substantially the same as the image sensor circuit block B1 and is similarly driven by the sawtooth wave generating circuit 4. Since the leak current of the photodiode of the dummy circuit block B0 is large or a constant light input is applied, this equivalent capacitance is discharged at the start of scanning by the sawtooth wave. When the scanning of the photodiode by the sawtooth wave is started, a charging current flows. This charging current is
It is the same as the output current when light is incident on the photodiode of the image sensor circuit block B1. Therefore,
The output current of the image sensor circuit block B1 can be appropriately sampled by the control signal formed based on the output current of the dummy circuit block B0. Also, a change in the phase of the sample and hold control signal is detected, and the slope of the sawtooth wave is controlled so as to suppress this change. Therefore, the change in tamming of the output of the sample and hold circuit is reduced. Further, by using the shift register, it becomes possible to output the output at a constant cycle.

[0008]

EXAMPLE A one-dimensional image sensor according to an example of the present invention will be described with reference to FIGS. The image sensor of FIG. 1 has first, second and third sensor circuit blocks B1, B2, B3. In FIG. 1, for convenience of illustration, 3
Only one sensor circuit block B1 to B3 is shown, but in reality more sensor circuit blocks are included. The image sensor of FIG. 1 further comprises a dummy circuit block B0 according to the invention. The circuit configuration of the dummy circuit block B0 is substantially the same as that of the sensor circuit blocks B1 to B3. Each of the blocks B0 to B3 has a sawtooth wave power supply terminal 1, a ground terminal (common power supply terminal) 2 and a common current output terminal 3.

The sawtooth wave generating circuit 4 repeatedly generates the sawtooth wave shown in FIG. In this embodiment, a typical sweep signal that linearly increases and then decreases is shown, but a waveform that increases stepwise and then decreases or that increases in a quadratic curve and then decreases. May be. Details of the sawtooth wave generation circuit 4 will be described later.

Since the dummy circuit block B0 is directly connected to the sawtooth wave generation circuit 4, the sawtooth wave shown in FIG. 10 (A) is directly input to the sawtooth wave generation circuit 4, and the sawtooth wave is repeatedly supplied. On the other hand, sensor circuit block B
A sawtooth wave is supplied to 1 to B3 via a demultiplexer 5. Under the control of the control circuit 11, the demultiplexer 5 extracts a sawtooth wave from the row of sawtooth waves in FIG. 10A and supplies it to the sensor circuit blocks B1 to B3 as shown in FIGS. To do. Therefore, the three output lines of the demultiplexer 5 are connected to the sawtooth power supply terminals 1 of the three sensor circuit blocks B1 to B3, respectively. The first sensor circuit block B1 is shown in FIG.
The sawtooth wave of 0 (B) is supplied, and the sawtooth wave of FIG. 10C is supplied to the second sensor circuit block B2.

The current output terminals 3 of the sensor circuit blocks B1 to B3 are commonly connected, and the current-voltage conversion circuit 7 is connected between the common current output line 6 and the ground. The output line of the current-voltage conversion circuit 7 is connected to the sample / hold circuit 8.

Current output terminal 3 of the dummy circuit block B0
The second current-voltage conversion circuit 9 is connected between the ground and the ground. The output line of the second current-voltage conversion circuit 9 is connected to the sample / hold control signal forming circuit 10. The control signal forming circuit 10 is a control circuit 1
The signal for controlling the sample and hold circuit 8 and the external circuit (not shown) is generated based on the control of 1.

The correction circuit 12 is provided to control the slope of the sawtooth wave generated from the sawtooth wave generation circuit 4. The inclination of the sawtooth wave is corrected so as to suppress the change in the generation timing of the sample hold control signal (sampling pulse). An external cook pulse input terminal 13 having a constant cycle is provided to detect a change in the sample and hold control signal.
And the correction circuit 12. In addition, the correction circuit 1
2 is connected to the output terminal of the sample and hold control signal forming circuit 10 by a line 14, and further, a line 15,
It is connected to the control circuit 11 by 16. The output terminal of the correction circuit 12 is connected to the sawtooth wave generation circuit 4. Details of the correction circuit 12 will be described later.

Each circuit block B0 to B3 in FIG. 1 is formed as shown in FIG. Although the first sensor circuit block B1 is shown in FIG. 2, the remaining sensor circuit blocks B2, B3 and the dummy circuit block B0 are also constructed in the same circuit. The circuit block B1 is composed of four unit circuits K0 and K1 corresponding to four pixels or bits connected between the sawtooth wave power source terminal 1 and the ground terminal 2.
, K2 and K3. One sensor circuit block B1 of the one-dimensional image sensor is configured to be able to detect 10 pixels. But,
Since it is difficult to show in the drawing all the unit circuits corresponding to all the pixels, only four of them are shown in FIG.

Three identical unit circuits K1, K2,
K3 is the first diode Da1, Da2, Da3, the second diode Db1, Db2, Db3 and the first resistor Ra1, Ra.
2, Ra3, second resistors Rb1, Rb2, Rb3, photodiodes S1, S2, S3, and blocking diodes Dc1, Dc2, Dc3. Another unit circuit K0
Comprises a second diode Db0, a first resistor Ra0, a photodiode S0 and a blocking diode Dc0. The unit circuit K0 is another unit circuit K1, K2, K
There is nothing corresponding to the first diodes Da1, Da2, Da3 and the second resistors Rb1, Rb2, Rb3 in 3.
However, the unit circuit K0 also has other unit circuits K1, K2, K
A third diode corresponding to the second resistor can be connected. Further, the unit circuit K0 of the first stage can be omitted from the image sensor of FIG. 2 if necessary.

An anode (first electrode) and a cathode (second electrode)
First electrodes Da1, Da with
One end (left end) of a circuit (first series circuit) in which 2 and Da3 are connected to each other in series is connected to the sawtooth wave power supply terminal 1. The first diodes Da1, Da2, Da3 have the directivity to be forward biased by the sawtooth voltage. That is, the anodes (first electrodes) of the first diodes Da1 to Da3 are arranged on the sawtooth wave power supply terminal 1 side. When a negative sawtooth wave is applied to the sawtooth power supply terminal 1, the first diodes Da1 to D1
The cathode of a3 is arranged on the side of the sawtooth power supply terminal 1.

The cathodes (second electrodes) of the first diodes Da1, Da2, Da3 and the common power supply terminal or ground terminal 2
A circuit (second series circuit) in which the first resistors Ra1, Ra2, Ra3 and the second diodes Db1, Db2, Db3 are connected in series is connected between and. In the unit circuit K0, a series circuit of a first resistor Ra0 and a second diode Db0 is connected between the sawtooth wave power supply terminal 1 and the ground terminal 2. The second diode Db0,
Db1, Db2, and Db3 have the directivity to be forward biased by the sawtooth wave.

The interconnection points P0, P1, Pb of the first resistors Ra0, Ra1, Ra2, Ra3 and the second diodes Db0, Db1, Db2, Db3 in each unit circuit K0, K1, K2, K3.
The cathodes of the photodiodes S0, S1, S2 and S3 are connected to 2 and P3, respectively. The anodes of the photodiodes S0, S1, S2, S3 are connected to a common current output terminal 3 via blocking diodes Dc0, Dc1, Dc2, Dc3 for preventing mutual interference of the photodiodes S0-S3. Since the current-voltage conversion circuit 7 or 9 is connected between the current output terminal 3 and the ground as shown in FIG.
Are substantially connected in parallel to the diodes Db0 to Db3. Since the photodiodes S0, S1, S2, and S3 are connected so as to be reverse-biased by the sawtooth wave, the current flowing there is extremely small.

The photodiodes S0 to S3, the first diodes Da1 to Da3, the second diodes Db0 to Db3, and the blocking diodes Dc0 to Dc3 are pin junction diodes, respectively, and are a hydrogenated alumophus silicon semiconductor layer. , One electrode layer provided below the semiconductor layer and the other electrode layer provided above the semiconductor layer, and provided on a common insulating substrate (not shown).
When the width given to each unit circuit K0 to K3 formed by the integrated circuit is 125 μm, the width of the wiring conductor layer of the first and second diodes Da1 to Da3 and Db0 to Db3 is about 2
It can be 0 μm. If the photodiode S
When the field effect transistor is used for scanning from 0 to S3, the width of the wiring conductor layer is about 10 .mu.m, which is narrower than that of the present embodiment, and the manufacturing yield of the image sensor is deteriorated.

The photodiodes S0 to S3 of the sensor circuit blocks B1 to B3 are formed with a small leak current, and are equivalently shown by a parallel circuit of the capacitance Cs and the current source Is proportional to the light intensity shown in FIG. . The value of the current flowing through the equivalent capacitance Cs of the photodiodes S0 to S3 is extremely small. On the other hand, since the photodiodes S0 to S3 of the dummy circuit block B0 have a large leak current, they can be represented by a parallel circuit of the capacitance Cs and the resistor R as shown in FIG. The photodiodes S0 to S3 of the dummy circuit block B0 are kept in a light-shielded state.

The both-end voltage when the first diodes Da1 to Da3 and the second diodes Db0 to Db3 are turned on, that is, the forward voltage Vf is approximately 1V. First resistor Ra0-
Ra3 is 100 kΩ each, and the second resistors Rb1 to Rb
Each b3 is 1 kΩ.

The first and second current-voltage conversion circuits 7 and 9 of FIG. 1 each include an operational amplifier (operational amplifier) 17 and a feedback resistor 18, as shown in FIG. One input terminal of the operational amplifier 17 is connected to the current output terminal 3, and the other input terminal is connected to the ground.

Sample and hold control signal forming circuit 10
Is a high-pass filter (HPF) 19 as shown in FIG.
And a comparator 20, a reference voltage source 21, a delay circuit 22, and a mono-multivibrator (MMV) 23. The high pass filter 19 is connected to the output terminal of the second current-voltage conversion circuit 9. The output terminal of the mono multivibrator 23 is connected to the sample and hold circuit 8.

The correction circuit 12 is 1/10 as shown in FIG.
It comprises a frequency divider 24, a 1/8 frequency divider 25, a phase comparator 26, an integrator 27, a reference voltage source 28 and an adder 29. 1 /
The input terminal of the frequency divider 10 is connected to the output line 14 of the sample and hold control signal forming circuit 10 of FIG. 1, and the reset terminal is connected to the reset signal line 15 of the control circuit 11. This 1/10 frequency divider 24 outputs the high level pulse (first frequency division) shown in FIG. 13D every time it counts 10 sample / hold control signals (sampling pulses) shown in FIG. 13B. Output) φ1 is generated,
3 (G), the sawtooth wave voltage Vd is reset in synchronization with the rising edge of the sawtooth wave voltage Vd. The 10 sample and hold control signals in FIG. 13B correspond to 10 photodiodes such as S0 to S3 as a matter of course.

The input terminal of the 1/8 frequency divider 25 is connected to the external clock pulse input terminal 13, and the reset terminal is connected to the reset line 16 of the control circuit 11. The external clock pulse is a pulse having a constant cycle as shown in FIG. 13A, and has a cycle longer than the cycle of the sample hold control signal of FIG. 13B by about 20%. The 1/8 frequency divider 25 outputs a high level pulse (second frequency division output) φ2 as shown in FIG. 13C when counting eight clock pulses after reset, and It is reset in synchronization with the rising of the sawtooth wave voltage Vd of (G).

One input terminal of the phase comparator 26 is 1/1
It is connected to the output terminal of the 0 frequency divider 24, and the other input terminal is connected to the output terminal of the 1/8 frequency divider 25. Therefore, the phase comparator 26 has a first frequency division output φ 1 shown in FIG. 13D and a second frequency division output φ shown in FIG. 13C.
A phase comparison output with 2 is generated as shown in FIG. Since the external clock pulse has a fixed period, the phase comparator 26 detects the phase change of the sample and hold control signal, that is, the change of the sampling period based on this. The sampling period is the first diodes Da1 to Da3.
It is caused by fluctuations in the forward voltage due to temperature changes such as.

The integrator 27 connected to the phase comparator 26 smoothes the phase comparison output of FIG. 13E to form the correction signal Va of FIG. 13F. The correction signal Va is added to the reference voltage Vr of the reference voltage source 28 in the adder 29 and supplied to the sawtooth wave generating circuit 4 on the line 29, which serves as the reference voltage source of the sawtooth wave generating circuit 4. In addition,
The sawtooth wave generation circuit 4 includes the reference voltage source 28 and the adder 29.
Can be connected to.

The sawtooth wave generating circuit 4 has an operational amplifier 30, an integrating capacitor 31, and an integrating capacitor 31, as shown in principle in FIG.
Input resistor 32, input switch 33, discharge resistor 34
, Discharge (reset) switch 35, and inverting amplifier 3
6 and the first, second and third mono-multivibrator 3
It consists of 7, 38 and 39. The negative input terminal of the operational amplifier 30 is connected to the correction circuit output line 29 via the input resistor 32 and the switch 33, and the positive input terminal is connected to the ground. The capacitor 31 is connected between the negative input terminal and the output terminal of the operational amplifier 30. The resistor 34 is connected in parallel to the capacitor 31 via the switch 35. An inverting amplifier 36 is connected to the output terminal of the operational amplifier 30. The sweep reference switch 33 is turned on in response to the sweep control signal of FIG. 9A generated from the first mono-multivibrator 37 for forming the sweep control signal. First mono-multivibrator 37 for forming sweep control signal
Is connected by line 40 to the control circuit 11 of FIG.
The pulse of FIG. 9A is generated in response to the sweep start timing signal supplied from here. During the ON period of the switch 33, the voltage Vr is output from the output line 29 of the correction circuit 12.
+ Va is applied, a charging current flows to the capacitor 31 via the resistor 32, and the integration operation of the capacitor 31 causes the charging current of FIG.
The ramp voltage in the section from t0 to t1 shown in (C) is obtained.
A second mono-multivibrator 38 for forming the hold-off control signal is connected to the first mono-multivibrator 37 and sets the period t1 to t2 in FIG. 9 in response to the trailing edge of the pulse obtained from this. The third mono-multivibrator 39 responds to the output of the second mono-multivibrator 38 to generate a pulse in the interval t2 to t3 shown in FIG. 9B. The switch 35 is a mono multivibrator 39.
In response to the output of, the signal is turned on in the section from t2 to t3 in FIG.
The electric charge of the capacitor 31 is discharged. It should be noted that the constant voltage section t1 to t2 in FIG. 9 is a period that can be omitted in principle, so that FIG. 10, FIG. 11, FIG. 12, FIG.
6 shows a sawtooth wave without a period corresponding to t1 to t2. The slope of the slope voltage obtained from the sawtooth wave generation circuit 4 changes as shown by the dotted line in FIG. 9C by the drive voltage Vr + Va supplied from the correction circuit 12. Since Va in the drive voltage Vr + Va changes according to the phase change of the sample and hold control signal as shown in FIG. 13F, the slope of the sawtooth wave changes so as to correct this phase change. This correction operation is shown in Figure 1.
As is clear from FIG. 3, it is performed for each sawtooth wave, that is, for each scan of one block. The sawtooth wave generation circuit 4 has a maximum amplitude value capable of turning on all the diodes Da1 to Da3 and Db0 to Db3, and the rising edges of the first and second diodes Da1 to Da3 and Db0 to Db3. Generate a sawtooth wave with a ramped voltage region that rises at a slower rate than the rate.

[0029]

[Operation] When the ramp voltage of the sawtooth wave voltage Vd supplied to the sensor circuit block of FIG. 2 gradually increases as shown in FIG. 11 (A), the potential Vp0 at the point P0 changes to that of FIG. 11 (B).
It gradually increases as shown in. As a result, when the potential Vp0 at the point P0 becomes the forward voltage Vf (about 1 V) of the second diode Db0 of the unit circuit K0, the diode Db0 is turned on, and the potential Vp0 at the point P0 is substantially constant (approximately Vf). )
That is, it becomes a saturation voltage value. At the same time as the second diode Db0 of the unit circuit K0 is turned on, the first diode Da1 of the unit circuit K1 is also turned on. While the first diode Da1 of the unit circuit K1 is non-conducting (OFF state), the cathode of the first diode Da1 is almost zero volt, but the first diode Da1 is turned on and the sawtooth wave is further generated. When the voltage Vd becomes higher, the cathode voltage of the first diode Da1 becomes higher following the sawtooth wave voltage Vd. That is, when the first diode Da1 is turned on, the voltage across the first diode Da1 is almost fixed to the forward voltage Vf. Therefore, the voltage obtained by subtracting the forward voltage Vf of the diode Da1 from the sawtooth voltage Vd is applied across the resistor Rb1. Join.
Further, the potential at the point P1 becomes substantially equal to the voltage across the second resistor Rb1 while the second diode Db1 of the unit circuit K1 is not conducting. Therefore, after the first diode Da1 is turned on, the potential Vp1 at the point P1 is changed to (B) in FIG.
It gradually rises as shown in. The potential Vp1 at the point P1 is the second
When the forward voltage Vf of the diode Db1 becomes the ON state, the potential Vp1 at the point P1 is substantially constant (Vf).
become. At about the same time that the second diode Db1 of the unit circuit K1 is turned on, the first diode Da2 of the unit circuit K2 is turned on, and the potential Vp2 is applied to the point P2 as shown in FIG. 11B. can get. When the sawtooth voltage further increases, the first diode Da3 of the unit circuit K3 is turned on, and the potential Vp3 of FIG. 11B is obtained at the point P3. When the potentials Vp0 to Vp3 of the points P0 to P3 change sequentially as shown in FIG. 11B, the points P0 to P3 are changed.
Photodiode S0 connected between the ground and ground
S3 is driven sequentially. That is, the photodiode S0
.About.S3 are electrically scanned.

The photodiodes S0 to S3 of the sensor circuit blocks B1 to B3 are arranged one-dimensionally. Photodiodes S0 to S3 of sensor circuit blocks B1 to B3
When reading the optical information, first, a sawtooth wave power supply terminal 1 is provided with a sawtooth wave having a maximum amplitude capable of turning on all the first diodes Da1 to Da3 and the second diodes Db0 to Db3. The voltage for turning on all the first diodes Da1 to Da3 and the second diodes Db0 to Db3 may be given by an independent circuit other than the sawtooth wave. At this time, the same voltage is applied to the dummy circuit block B0.

During the period when all of the first diodes Da1 to Da3 and the second diodes Db0 to Db3 are in the ON state,
The forward voltage Vf (about 1 V) of the second diodes Dbo to Db3 obtained at the points P0 to P3 reverse-biases the photodiodes S0 to S3 to charge the capacitance Cs equivalently shown in FIG.

An optical signal obtained from a subject (not shown) such as a document of a facsimile, which is arranged opposite to the sensor circuit block B1 of FIG.
When input to 0 to S3, the equivalent capacitance C of the photodiodes S0 to S3 depends on the presence or absence of an optical signal and its magnitude.
The charge amount of s changes. That is, the photodiode S
In the range of 0 to S3, the equivalent capacitance Cs is discharged in the case where the optical signal is input, and the equivalent capacitance Cs is not generated in the case where the optical signal is not input. The amount of discharge of the equivalent capacitance Cs changes depending on the amount of light. There are two methods of applying an optical input to the photodiodes S0 to S3. One is the photodiode S0 ~
This is a method in which an optical input is always applied to S3, and the other is a method in which an optical input is applied only during a predetermined period (for example, a period when the sawtooth wave voltage Vd is zero volt).

When the sawtooth voltage Vd increases linearly with time as shown in FIG. 11 (A), points P0 to P3.
As shown in FIG. 11B, the potentials Vp0, Vp1, Vp2,
Vp3 is obtained, which allows photodiodes S0 ...
S3 is reverse biased sequentially. In other words, the voltage for charging the equivalent capacitance Cs shown in FIG. 3 is applied to the photodiodes S0 to S3. At this time, a charging current flows through the equivalent capacitance Cs of the photodiodes S0 to S3 which is discharged by optical input,
The charging current does not flow to those that have not been discharged due to no light input. The charging current of the equivalent capacitance Cs of the photodiodes S0 to S3 is the blocking diode Dc0.
Since it flows through ~ Dc3 and the current-voltage conversion circuit 7,
The output voltage of the current-voltage conversion circuit 7 is the photodiode S.
It varies depending on the presence or absence of the charging current of the equivalent capacitance Cs of 0 to S3. In FIG. 11C, the combined output current Iout of the photodiodes S0 to S3, that is, the current output terminal 3 is shown.
Current is shown. In FIG. 11C, the combined output current I0ut when there is a large light input to the three photodiodes S0, S1 and S3 and a small light input to one photodiode S2. It is shown. The output current I0ut is the potential Vp0 of each point P0-P3.
It increases following the rise of Vp3 and decreases when the potentials Vp0 to Vp3 approach saturation.

The sample and hold circuit 8 samples the output current Iout of FIG. 11C in synchronization with the rising edge of the control signal Vs shown in FIG. 11D. That is, the vicinity of the peak value of the AC component generated based on the scanning of the photodiodes S0 to S3 is sampled. Output current I0ut
The peaks of do not always occur regularly in a certain cycle. Therefore, in this embodiment, the dummy circuit block B0 is provided, and the sampling timing is determined based on this output. The output voltage V0ut shown in FIG. 11E is obtained at the output terminal of the sample and hold circuit 8.
This corresponds to the light input of the photodiodes S0 to S3.

FIG. 12 shows the operation of forming the sample and hold control signal based on the dummy circuit block B0.
Since the circuit configuration of the dummy circuit block B0 is substantially the same as that of the sensor circuit blocks B1 to B3, the dummy circuit block B0 will be described with reference to the circuit of FIG. When a sawtooth voltage is applied to the dummy circuit block B0 as shown in FIG. 12A, the photodiodes S0 to S3 are scanned similarly to the sensor circuit blocks B1 to B3. Since the photodiodes S0 to S3 of the dummy circuit block B0 have a large leak current as shown in FIG. 4, the equivalent capacitance C at the start of scanning is in spite of being in the light-shielded state.
s is discharged. Therefore, when scanning is started, as shown in FIG.
In the sensor circuit block B1 to B3 shown in FIG. 2B, a current Idm similar to the output current Iout when light input is given to all the photodiodes S0 to S3. The output current Idm of the dummy circuit block B0 shown in FIG. 12C is converted into a voltage by the second current-voltage conversion circuit 9, and this voltage is input to the high-pass filter 19 of FIG. As a result, the alternating current component of the dummy current detection signal is obtained from the high pass filter 19 as shown in FIG. This AC component is compared with the reference voltage by the comparator 20, and the waveform is shaped as shown in FIG. The comparator output pulse of FIG. 12 (E) is delayed by the delay circuit 22 so that this leading edge substantially coincides with the current peak of FIG. 12 (B). The output of the delay circuit 22 triggers the mono-multivibrator 23 from which the sample and hold control signal shown in FIG. The extra pulse generated at the end of scanning is masked by the control circuit 11 so as not to be output. If the sample and hold control signal is formed based on the dummy circuit block B0 having substantially the same structure as the sensor circuit blocks B1 to B3, the control signal with the optimum timing can be easily obtained.

As already described, the first diode Da1
When the temperature of ~ Da3 changes, this forward voltage changes,
The scanning speed of the photodiodes S0 to S3 changes. The correction circuit 12 works to prevent this change. FIG. 13 shows FIG.
The operation of the correction circuit 12 is shown. 1/8 frequency divider 25 is shown in FIG.
When eight (3) (A) clock pulses are input, as shown in FIG.
The divided output pulse .phi.2 shown in (C) of FIG. 1/1
The 0 frequency divider 24 generates the frequency-divided output pulse .phi.1 shown in FIG. 13D when ten sampling pulses shown in FIG. 13B are input. The two frequency dividers 24 and 25 are shown in FIG.
The reset pulse is synchronized with the rising edge of the sawtooth voltage Vd shown in (G) of 3 and the subsequent input pulses are counted. The phase comparator 26 generates a pulse corresponding to the phase difference of the leading edge (leading edge) between the pulse φ2 in FIG. 13C and the pulse φ1 in FIG. 13D as shown in FIG. 13E. The phase comparison output of (E) is smoothed by the integrator 27 and becomes the correction signal Va shown in (F) of FIG. This correction signal Va is added to the reference voltage Vr and becomes the drive voltage of the sawtooth wave generation circuit 4. Sawtooth generation circuit 4 shown in FIG.
If the driving voltage Vr + Va of the line 29 of FIG.
(G), the slope of the sawtooth voltage Vd changes, and a sawtooth voltage Vd that compensates for the change in the forward voltage of the first diodes Da1 to Da3 is generated. As a result, fluctuations in the sampling pulse generation interval shown in FIG. 13B are reduced. Since the correction signal Va is zero during the first generation of the sawtooth voltage, it is desirable to generate the sawtooth wave and stabilize the generation of the sampling pulse before the reading by the photodiodes S0 to S3.

Next, an image sensor of another embodiment shown in FIGS. 14 to 16 will be described. However, in FIG. 14, except for the shift register 50, the configuration is the same as that of FIG. 1, and thus the common portions are denoted by the same reference numerals and the description thereof is omitted. The analog shift register 50 is connected to the sample and hold circuit 8 and adjusts the output timing of the photodiodes S0 to S3. To control the shift register 50, the sample and hold control signal forming circuit 10 is connected here by a line 51, and the control circuit 11 is connected by a line 52.
, And the external clock pulse terminal 13 is also connected by a line 53.

The analog shift register 50 includes first and second shift registers 50a and 50b and first to eighth switches S1 to S1 ... Which are arranged in parallel as shown in principle in FIG.
It consists of S8. The first and second shift registers 50a,
50b has a capacity capable of storing the output of one sensor circuit block. The input terminals of the first and second shift registers 50a and 50b are connected to the output line 54 of the sample and hold circuit 8 via the switches S1 and S2, and the output terminals are connected to the output terminal 5 via the switches S3 and S4.
Connected to 5. The write clock terminals of the shift registers 50a and 50b are connected to the sampling pulse line 51 via the switches S5 and S6. The read clock terminals of the shift registers 50a and 50b are connected to the external clock pulse line 53 through the switches S7 and S8.
It is connected to the. The switches S1 to S8 are turned on / off based on the control signal given from the line 52 as shown in FIG.

As is apparent from FIG. 16, the switches S1, S4, S5 and S8 are turned on while the sensor circuit block B1 is being scanned based on the sawtooth voltage Vd. As a result, the output of the first sensor circuit block B1 is written in the first shift register 50a in synchronization with the sampling pulse. At this time, the second shift register 5
0b is the read mode. Next, while the second sensor circuit block B2 is being scanned, the switch S2
, S3, S6 and S7 are turned on. As a result, the output signal of the second sensor circuit block B2 is written in the second shift register 50b, and the first shift register 50a
From the output signal of the first sensor circuit block B1 is read by the external clock. By repeating such operations, it is possible to obtain a sensor output synchronized with the external clock.

[0040]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.

The plurality of sensor circuit blocks B1 to B3 can be divided into an odd number and an even number so as to be driven alternately.

It is possible to connect the cathodes of the second diodes Db0 to Db3 in FIG. 2 in common, and to apply a sawtooth wave and a bias voltage having a reverse slope between this common connection point and the ground.

It is also possible to divide the sensor circuit blocks B1 to B3 into a plurality of sections and provide a dummy circuit block B0 for each to perform sample and hold control. Further, a dedicated sawtooth wave generating circuit may be provided for the dummy circuit block B0.

The photodiodes S0 to S3 of the dummy circuit block B0 may be provided with a constant intensity of light input. In this case, the photodiodes S0 to S3 of the dummy circuit block B0 are connected to the sensor circuit block B1 to
It can be configured identically to that of B3.

The current-voltage conversion circuits 7 and 9 can be composed of current detection resistors or the like.

As shown in FIG. 17, the second resistor Rb1 of FIG.
~ Rb3 can be replaced by capacitors Cb1 to Cb3. Note that the capacitors Cb1 to Cb3 may be replaced with diodes of reverse bias connection and the capacitance of these diodes may be used.

As shown in FIG. 18, the first resistor Ra0 of FIG.
.About.Ra3 can be replaced by capacitors C1 to C3 and the second diodes Db1 to Db3 can be replaced by resistors R1 to R3. The capacities of the capacitors C1 to C3 are made sufficiently larger than the equivalent capacities of the photodiodes S0 to S3. Alternatively, the capacitors C1 to C3 may be replaced with diodes connected in reverse bias polarity, and the capacitance of the diodes may be used as capacitors.

Blocking diodes Dc0 to Dc3 for preventing mutual interference of the photodiodes S0 to S3 are connected in series to the first resistors Ra1 to Ra3, or the second resistors Rb1 to Rb3 and the first resistors Ra1 to Ra1. It is possible to connect to Ra3.

The polarity of each diode and the sawtooth wave can be reversed.

[0050]

According to the present invention, stabilization of the output cycle of the photodiode is achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image sensor according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing in detail a sensor circuit block of FIG.

3 is an equivalent circuit diagram of a photodiode of the sensor circuit block of FIG.

FIG. 4 is an equivalent circuit diagram of a photodiode of the dummy circuit block of FIG.

5 is a circuit diagram showing the current-voltage conversion circuit of FIG.

6 is a block diagram showing a sample and hold control signal forming circuit of FIG. 1. FIG.

7 is a block diagram showing the correction circuit of FIG. 1. FIG.

8 is a block diagram showing the sawtooth wave generation circuit of FIG. 1. FIG.

FIG. 9 is a waveform diagram showing a state of each part of FIG.

10 is a waveform diagram showing input / output of the demultiplexer of FIG.

FIG. 11 is a waveform chart showing a state of each part of FIG.

12 is a waveform diagram showing the output of the sawtooth wave generation circuit of FIG. 1, the output currents of the sensor circuit block and the dummy circuit block, and the states of the respective parts of the sample and hold circuit of FIG.

13 is a waveform diagram showing a state of each part of the correction circuit of FIG. 7 and a sawtooth voltage.

FIG. 14 is a block diagram showing an image sensor of another embodiment.

15 is a circuit diagram showing the shift register of FIG. 14 in principle.

FIG. 16 is a circuit diagram illustrating an example in which the switch of the shift register in FIG.
It is a wave form diagram which shows OFF and a sawtooth voltage.

FIG. 17 is a circuit diagram showing a sensor circuit block of a modified example.

FIG. 18 is a circuit diagram showing a sensor circuit block of another modification.

[Explanation of symbols]

 4 sawtooth wave generation circuit 7 first current-voltage conversion circuit 8 sample and hold circuit 9 second current-voltage conversion circuit 10 sample and hold control signal forming circuit 12 correction circuit

Claims (5)

(57) [Claims] 1. A sawtooth wave generation circuit (4) for periodically generating a sawtooth wave, an image sensor circuit block (B1), and a timing signal forming device having substantially the same configuration as the image sensor circuit block (B1). Dummy circuit block (B
0), a first current-voltage conversion circuit (7) connected to the image sensor circuit block (B1), and a sample-hold circuit (7) connected to the first current-voltage conversion circuit (7). 8), a second current-voltage conversion circuit (9) connected to the dummy circuit block (B0), and the sample-hold circuit based on the output of the second current-voltage conversion circuit (9). (8) A sample and hold control signal forming circuit (10) for forming a sample and hold control signal, wherein the image sensor circuit block (B1) and the dummy circuit block (B0) are respectively provided with a first A plurality of first electrodes each having an electrode and a second electrode
Is a circuit in which the diodes (Da1 to Da3) are connected in series, one end of which is connected to the sawtooth wave generating circuit,
Further, the plurality of first diodes (Da1 to Da3) have directivity such that forward currents of the plurality of first diodes (Da1 to Da3) flow based on the sawtooth wave,
A first series circuit in which the first electrodes of the plurality of first diodes (Da1 to Da3) are arranged on the sawtooth wave generation circuit side, and first resistors (Ra1 to Ra3), respectively. ) Or a first impedance element composed of a first capacitor (C1 to C3) and a second diode (Db1 to Db3) or a resistor (R1 to R3) connected in series. Diode (Da1
~ Da3) the second electrode and a common power supply terminal (ground)
And a plurality of second diodes (Db1 to Db3) having directivity such that forward currents of the plurality of second diodes (Db1 to Db3) flow based on the sawtooth wave. A plurality of second series circuits, and the plurality of first diodes (Da1 to Da3) of the second series circuits.
Second resistances (Rb1 to Rb3) or second resistances respectively connected between the electrodes of the
Second impedance element composed of the capacitors (Cb1 to Cb3), one end of which is connected between the first impedance element and the second diode (Db1 to Db3) or the resistors (R1 to R3), respectively. The other end is composed of a plurality of photodiodes (S1 to S3) commonly connected to each other, and the photodiodes (S1 to S3) of the dummy circuit block (B0) are the image sensor circuit blocks (B1 to B3). Of the photodiodes (S1 to S3)
The leakage current is larger than that of the first and second current-voltage conversion circuits (7) and (9).
Are respectively connected between a common connection point of the other ends of the plurality of photodiodes (S1 to S3) in the image sensor circuit block (B1) and the dummy circuit block (B0) and the common power supply terminal (ground). The sample and hold control signal forming circuit (10) is
The sample / hold control signal is formed based on an AC component indicating scanning of the photodiodes (S1 to S3) obtained from the second current-voltage conversion circuit (9), and a clock is generated at a constant cycle. Clock pulse generating means for generating a pulse is provided, the phase change of the sample and hold control signal is detected with reference to the clock pulse to form a correction signal, and the phase change is caused by the change of the slope of the sawtooth wave. An image sensor, comprising a correction circuit for controlling the sawtooth wave generation circuit with the correction signal so as to perform correction. 2. A shift register connected to the sample and hold circuit, wherein the shift register writes the output of the sample and hold circuit in synchronization with the sample and hold control signal to write the clock pulse. The image sensor according to claim 1, wherein the image sensor is configured to perform reading based on the reading. 3. A photodiode (S) having a large leak current in the dummy circuit block (B0) according to claim 1 or 2.
1-S3), instead of the photodiodes (Da1-Da3) of the image sensor circuit block (B1), a photodiode having substantially the same structure and a leak circuit connected in parallel with the photodiode are used. An image sensor characterized in that 4. The image sensor according to claim 1, wherein the plurality of photodiodes (S1 to S3) of the dummy circuit block (B0) are kept in a light-shielded state. 5. The photodiode (S) having a large leak current in the dummy circuit block (B0) according to claim 1 or 2.
1 to S3), instead of the image sensor circuit block (B1), a photodiode having substantially the same structure as the photodiodes (S1 to S3) is provided, and a constant light input is given to this photodiode. Image sensor.