JPS6316910B2 - - Google Patents

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Publication number
JPS6316910B2
JPS6316910B2 JP53103533A JP10353378A JPS6316910B2 JP S6316910 B2 JPS6316910 B2 JP S6316910B2 JP 53103533 A JP53103533 A JP 53103533A JP 10353378 A JP10353378 A JP 10353378A JP S6316910 B2 JPS6316910 B2 JP S6316910B2
Authority
JP
Japan
Prior art keywords
charge
transfer
input
channel
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53103533A
Other languages
Japanese (ja)
Other versions
JPS5529191A (en
Inventor
Ikuo Akyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP10353378A priority Critical patent/JPS5529191A/en
Publication of JPS5529191A publication Critical patent/JPS5529191A/en
Publication of JPS6316910B2 publication Critical patent/JPS6316910B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/762Charge transfer devices
    • H01L29/765Charge-coupled devices
    • H01L29/768Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76808Input structures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Filters That Use Time-Delay Elements (AREA)

Description

【発明の詳細な説明】 本発明は電荷結合素子に関し、さらに詳しくは
複数チヤネル構造を有する電荷結合素子における
バイアス電荷注入法の改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to charge coupled devices, and more particularly to improvements in bias charge injection methods in charge coupled devices having a multi-channel structure.

従来、電荷結合素子を応用した装置、たとえば
遅延線、一次元イメージセンサ等の転送部の構造
としてデユアルチヤネル構造が知られている。転
送部へ供給する転送パルスの繰り返し周波数を同
一と仮定して前記構造をモノチヤネル構造と比べ
た場合、ナイキスト限界は2倍になり、同一の遅
延時間を得るための転送段数及び消費電力は2分
の1となる。しかしながら、従来のデユアルチヤ
ネル型電荷結合素子では、各チヤネルに入出力部
が個々にあるためにチヤネル間の入出力特性に差
が生じるという欠点があつた。
Conventionally, a dual channel structure has been known as a structure of a transfer section of a device to which a charge-coupled device is applied, such as a delay line or a one-dimensional image sensor. When comparing the above structure with a monochannel structure assuming that the repetition frequency of the transfer pulses supplied to the transfer section is the same, the Nyquist limit is doubled, and the number of transfer stages and power consumption to obtain the same delay time are doubled. 1. However, conventional dual-channel charge-coupled devices have a drawback in that each channel has an individual input/output section, resulting in differences in input/output characteristics between the channels.

この欠点を解決する方法として、各転送チヤネ
ルに共通な電荷入力部と単一の出力部をもつ第1
図に示すようなデユアルチヤネル型電荷結合素子
が提案された。即ち、転送チヤネルに共通な電荷
入力部はインプツトダイオード11とデユアル入
力ゲート電極12,13とスイツチングゲート電
極14とで構成され、出力部はチヤネルに共通な
浮遊拡散層15と出力アンプ16で構成されてい
る。17,18は転送チヤネルの第1電極であ
る。代表的な電荷注入方法として、インプツトダ
イオード11にサンプリングパルス、入力ゲート
電極12に信号と直流バイアス、入力ゲート電極
13に直流バイアスを印加する電位平衡法が周知
であり、入力ゲート電極13下に蓄積された信号
電荷とバイアス電荷とはスイツチングゲート電極
14に転送チヤネルの第1電極17及び18に印
加する転送パルスと同期したパルスを印加するこ
とにより、二つの転送チヤネルに交互に注入され
る。二つの転送チヤネルを転送されて来た信号電
荷とバイアス電荷とは浮遊拡散層15の電位を交
互に変化させ、この変化分は出力アンプ16によ
り検出される。第2図は第1図で示したデユアル
チヤネル型電荷結合素子の出力部を説明するため
の図であり、21は転送チヤネルAの最終電極、
22は転送チヤネルBの最終電極、23は出力端
子を示し、第1図と同一な番号は同一のものを示
す。同図に示すように、出力部においては様々な
結合容量が存在し、たとえば転送チヤネルAの最
終電極21と浮遊拡散層15との間には結合容量
C1が、同様に出力アンプ16との間に結合容量
C2が、出力端子23との間に結合容量C3などが
存在する。転送チヤネルBについても同様に最終
電極22と浮遊拡散層15との間には結合容量
C1′が、出力アンプ16との間に結合容量C2′が、
出力端子23との間に結合容量C3′などが存在す
る。これらは出力部に存在する結合容量のごく一
部である。ここでは簡単のため転送パルスφ1
印加される電極と浮遊拡散層15と出力アンプ1
6及び出力端子23などで構成される出力部との
間の結合容量の合計をC〓1、転送パルスφ2が印加
される電極と出力部との間の結合容量の合計を
C〓2とすると、一般にC〓1≠C〓2であるために、転
送パルスφ1あるいは転送パルスφ2が出力信号波
形に与える影響はそれぞれ異なり、第3図で示す
ように出力信号波形の出力レベルに差が生じる。
このことは出力信号にクロツクパルス周波数(ナ
イキスト限界)の成分が含まれていることにな
る。転送パルスが出力信号波形に与える影響はそ
の繰り返し周波数が高くなるほど顕著になり、電
荷結合素子をTVビデオ信号処理の分野などのよ
うに高周波で動作させなければならない分野に応
用する場合に大きな問題となる。
A method to overcome this drawback is to use a first charge input with a common charge input and a single output for each transfer channel.
A dual-channel charge-coupled device as shown in the figure was proposed. That is, the charge input section common to the transfer channel is composed of an input diode 11, dual input gate electrodes 12 and 13, and a switching gate electrode 14, and the output section is composed of a floating diffusion layer 15 and an output amplifier 16 common to the channels. It is configured. 17 and 18 are first electrodes of the transfer channel. As a typical charge injection method, a potential balancing method is well known in which a sampling pulse is applied to the input diode 11, a signal and DC bias is applied to the input gate electrode 12, and a DC bias is applied to the input gate electrode 13. The accumulated signal charge and bias charge are alternately injected into the two transfer channels by applying a pulse to the switching gate electrode 14 that is synchronized with the transfer pulse applied to the first electrodes 17 and 18 of the transfer channel. . The signal charges and bias charges transferred through the two transfer channels alternately change the potential of the floating diffusion layer 15, and this change is detected by the output amplifier 16. FIG. 2 is a diagram for explaining the output section of the dual channel charge coupled device shown in FIG. 1, where 21 is the final electrode of transfer channel A;
22 is the final electrode of the transfer channel B, 23 is the output terminal, and the same numbers as in FIG. 1 indicate the same items. As shown in the figure, there are various coupling capacitances in the output section. For example, there is a coupling capacitance between the final electrode 21 of transfer channel A and the floating diffusion layer 15.
Similarly, C 1 has a coupling capacitance between it and the output amplifier 16.
A coupling capacitance C 3 exists between C 2 and the output terminal 23 . Similarly, for transfer channel B, there is a coupling capacitance between the final electrode 22 and the floating diffusion layer 15.
A coupling capacitance C 2 ′ exists between C 1 ′ and the output amplifier 16.
A coupling capacitance C 3 ' exists between the output terminal 23 and the output terminal 23. These are only a small portion of the coupling capacitance present at the output. Here, for simplicity, we will explain the electrode to which the transfer pulse φ 1 is applied, the floating diffusion layer 15, and the output amplifier 1.
C〓 1 is the total coupling capacitance between the electrode 6 and the output section consisting of the output terminal 23, etc., and the total coupling capacitance between the electrode to which the transfer pulse φ2 is applied and the output section is C〓 1 .
If C〓 2 , generally C〓 1 ≠ C〓 2 , so the influence of transfer pulse φ 1 or transfer pulse φ 2 on the output signal waveform is different, and as shown in Fig. 3, the influence of the output signal waveform is A difference occurs in the output level.
This means that the output signal contains a component of the clock pulse frequency (Nyquist limit). The effect that the transfer pulse has on the output signal waveform becomes more pronounced as its repetition frequency increases, and this becomes a major problem when applying charge-coupled devices to fields that require high-frequency operation, such as TV video signal processing. Become.

第1図に示すような構造においては入出力部の
違いによる各転送チヤネルの出力電圧のばらつき
は解消されるものの、各転送チヤネル間で暗電流
及び転送効率が異なるために発生する出力電圧の
ばらつきや、第2図,第3図で説明した出力部の
結合容量による出力電圧のばらつきは電荷結合素
子の駆動法により改善することはできず、そのば
らつきの程度は電荷結合素子の製造工程にのみ依
存し、最悪の場合は各転送チヤネルの出力電圧間
で20%程度の差異があつた。
In the structure shown in Figure 1, variations in the output voltage of each transfer channel due to differences in input/output sections are eliminated, but variations in output voltage that occur due to differences in dark current and transfer efficiency between each transfer channel are eliminated. Also, the variation in output voltage due to the coupling capacitance of the output section explained in Figures 2 and 3 cannot be improved by the driving method of the charge-coupled device, and the extent of the variation can only be determined by the manufacturing process of the charge-coupled device. In the worst case, there was a difference of about 20% between the output voltages of each transfer channel.

本発明はこのような従来の欠点を除去し、転送
チヤネル間ばらつきの少ない複数チヤネル型電荷
結合素子を提供することを目的とする。
An object of the present invention is to eliminate such conventional drawbacks and provide a multi-channel charge-coupled device with less variation between transfer channels.

本発明によれば、インプツトダイオードと第1
および第2の入力ゲート電極とスイツチングゲー
ト電極とで構成された電荷入力部と、該電荷入力
部からの信号電荷を複数列に分けてそれぞれ位相
の異なる転送パルスで転送する電荷転送チヤネル
と、該複数列の電荷転送チヤネルからの信号電荷
を合成出力する電荷出力部とを有する電荷結合素
子において、前記第1および第2の入力ゲート電
極のうちいずれか一方を前記複数列の電荷転送チ
ヤネルのそれぞれに対応して独立な電気信号が印
加されるように分割し、これら分割された入力ゲ
ート電極のそれぞれに前記複数列の電荷転送チヤ
ネルからの信号出力電圧のばらつきが補正される
ようなそれぞれ異なる直流バイアス電圧を印加す
ることを特徴とする電荷結合素子が得られる。
According to the invention, the input diode and the first
and a charge input section composed of a second input gate electrode and a switching gate electrode, and a charge transfer channel that divides signal charges from the charge input section into a plurality of columns and transfers them using transfer pulses having different phases, respectively. In the charge-coupled device having a charge output section that synthesizes and outputs signal charges from the plurality of rows of charge transfer channels, one of the first and second input gate electrodes is connected to one of the plurality of rows of charge transfer channels. The divided input gate electrodes are divided so that independent electrical signals are applied thereto, and different electrical signals are applied to each of the divided input gate electrodes so that variations in the signal output voltage from the plurality of charge transfer channels are corrected. A charge-coupled device characterized in that a DC bias voltage is applied is obtained.

以下図面を参照して本発明による複数チヤネル
型電荷結合素子を説明する。
A multi-channel charge coupled device according to the present invention will be described below with reference to the drawings.

第4図は本発明の一実施例を示したもので、4
1a,41bは二つに分割された入力ゲート電
極、42の点線部分はチヤネルストツパーを示
す。また43は入力ゲート電極41a,41bに
直流バイアスを印加するための電圧源、44は入
力ゲート電極41a,41bに印加される直流バ
イアスを調整するための可変抵抗を示す。第1図
と同一な番号は同一のものを示す。
FIG. 4 shows an embodiment of the present invention.
Reference numerals 1a and 41b indicate input gate electrodes divided into two parts, and a dotted line portion 42 indicates a channel stopper. Further, 43 represents a voltage source for applying a DC bias to the input gate electrodes 41a and 41b, and 44 represents a variable resistor for adjusting the DC bias applied to the input gate electrodes 41a and 41b. The same numbers as in FIG. 1 indicate the same things.

次にこの実施例の動作を説明する。まず電荷の
注入にはインプツトダイオード11にサンプリン
グパルス、入力ゲート電極41a,41bにそれ
ぞれ異なる直流バイアス、入力ゲート電極13に
信号と直流バイアスを印加する電位平衡法が用い
られ、これにより入力ゲート電極13下には信号
電荷とバイアス電荷が蓄積される。次に転送チヤ
ネルの第1電極17,18には180゜位相の異なる
転送パルスφ1,φ2が印加されているので、スイ
ツチングゲート電極14に上記の二つの転送パル
スに同期したパルスを印加することにより、入力
ゲート電極13下の領域45と領域46に蓄積さ
れた電荷は交互にそれぞれ転送チヤネルA,転送
チヤネルBに注入される。第5図は、入力ゲート
電極に印加する直流バイアスと転送チヤネルに注
入される電荷量の関係を示す図で、入力ゲート電
極41a,41bに印加される直流バイアスを
VG1,転送チヤネルに注入される電荷量をQとし
てある。またVA,VBはそれぞれ入力ゲート電極
41a,41bに印加される直流バイアス,QA
QBはそれぞれ転送チヤネルA,Bに注入される
電荷量を示す。入力ゲート電極13に印加される
直流バイアスVG2は一定としてある。同図から明
らかなように、第4図の可変抵抗44を用いて入
力ゲート電極41a,41bに印加される直流バ
イアスVA,VBを異なる値に設定することになり、
転送チヤネルA,Bにそれぞれ異なるバイアス電
荷QA,QBを注入することができる。また第5図
に示す直流バイアスVG1と転送チヤネルに注入さ
れる電荷量Qとの関係が線形である限り、同一の
入力信号レベルに対して転送チヤネルA及びBへ
注入される信号電荷の量は等しい。
Next, the operation of this embodiment will be explained. First, for charge injection, a potential balancing method is used in which a sampling pulse is applied to the input diode 11, different DC biases are applied to the input gate electrodes 41a and 41b, and a signal and DC bias are applied to the input gate electrode 13. Signal charges and bias charges are accumulated below 13. Next, since the transfer pulses φ 1 and φ 2 having a phase difference of 180° are applied to the first electrodes 17 and 18 of the transfer channel, a pulse synchronized with the above two transfer pulses is applied to the switching gate electrode 14. As a result, charges accumulated in regions 45 and 46 under input gate electrode 13 are alternately injected into transfer channel A and transfer channel B, respectively. FIG. 5 is a diagram showing the relationship between the DC bias applied to the input gate electrodes and the amount of charge injected into the transfer channel.
V G1 and the amount of charge injected into the transfer channel is Q. Further, V A and V B are DC biases applied to the input gate electrodes 41a and 41b, respectively, and Q A ,
Q B indicates the amount of charge injected into transfer channels A and B, respectively. The DC bias V G2 applied to the input gate electrode 13 is constant. As is clear from the figure, the DC biases V A and V B applied to the input gate electrodes 41a and 41b are set to different values using the variable resistor 44 in FIG.
Different bias charges Q A and Q B can be injected into the transfer channels A and B , respectively. Furthermore, as long as the relationship between the DC bias V G1 and the amount of charge Q injected into the transfer channel shown in FIG. 5 is linear, the amount of signal charge injected into transfer channels A and B for the same input signal level. are equal.

したがつて、各転送チヤネルの出力電圧が均一
となるように可変抵抗44を調整すれば、すなわ
ち、出力電圧の小さい方の転送チヤネルに対応す
る入力ゲート電極(41aまたは41b)に他方
より小さい直流バイアスを印加すれば、この転送
チヤネルには他の転送チヤネルより多くのバイア
ス電荷が注入されるので、各転送チヤネルの暗電
流、転送効率のばらつきや、出力部での結合容量
の違いによつて生じる各転送チヤネルの出力電圧
のばらつきが補正され、第6図に示すような均一
な出力電圧を得ることができる。
Therefore, if the variable resistor 44 is adjusted so that the output voltage of each transfer channel is uniform, that is, a DC voltage smaller than that of the other transfer channel is applied to the input gate electrode (41a or 41b) corresponding to the transfer channel with the smaller output voltage. When a bias is applied, more bias charge is injected into this transfer channel than other transfer channels, so the dark current of each transfer channel, variations in transfer efficiency, and differences in coupling capacitance at the output section Variations in the output voltage of each transfer channel that occur are corrected, and a uniform output voltage as shown in FIG. 6 can be obtained.

なお、第4図の構成においては入力ゲート電極
41a,41bにそれぞれ異なる直流バイアス、
入力ゲート電極13に信号と直流バイアスを印加
しているが、この二つの電極の順序を逆にした第
7図のような構成でも、第4図とまつたく同様な
効果が得られる。第7図において71a,71b
は二つに分割された入力ゲート電極を示し、第4
図と同一な番号は同一のものを示す。
In the configuration shown in FIG. 4, the input gate electrodes 41a and 41b are provided with different DC biases,
Although a signal and a DC bias are applied to the input gate electrode 13, a configuration as shown in FIG. 7 in which the order of these two electrodes is reversed can also provide the same effect as in FIG. 4. 71a, 71b in FIG.
indicates an input gate electrode divided into two, and the fourth
Numbers that are the same as those in the figures indicate the same items.

また、第8図は本発明を三列転送チヤネル型電
荷結合素子に応用した一実施例を示したもので、
81a,81b,81cは三つに分割された入力
ゲート電極、82は転送チヤネルCの第1電極、
83a,83b,83cはそれぞれ入力ゲート電
極81a,81b,81cに印加される直流バイ
アスを調整するための可変抵抗を示す。第4図と
同一な番号は同一なものを示す。同図において、
各転送チヤネルの出力電圧が均一となるように可
変抵抗83a,83b,83cを調整すれば、す
なわち、出力電圧の小さい転送チヤネルにより多
くのバイアス電荷が注入されるように3つの可変
抵抗83a,83b,83cを調整すれば、各転
送チヤネルの暗電流、転送効率のばらつきや、出
力部での結合容量の違いによつて生じる各転送チ
ヤネルの出力電圧のばらつきが補正される。
FIG. 8 shows an embodiment in which the present invention is applied to a three-row transfer channel type charge coupled device.
81a, 81b, 81c are input gate electrodes divided into three; 82 is a first electrode of transfer channel C;
Reference numerals 83a, 83b, and 83c indicate variable resistors for adjusting the DC bias applied to the input gate electrodes 81a, 81b, and 81c, respectively. The same numbers as in FIG. 4 indicate the same parts. In the same figure,
If the variable resistors 83a, 83b, 83c are adjusted so that the output voltage of each transfer channel is uniform, that is, the three variable resistors 83a, 83b are adjusted so that more bias charge is injected into the transfer channel with a lower output voltage. , 83c, the dark current of each transfer channel, variations in transfer efficiency, and variations in output voltage of each transfer channel caused by differences in coupling capacitance at the output section can be corrected.

以下同様に、複数チヤネル構造を有する電荷結
合素子においても、電荷入力部のいずれか一つの
入力ゲート電極を転送チヤネルに等しい数だけ電
荷転送方向に分割し、分割されたそれぞれの入力
ゲート電極に適切な直流バイアスを印加すること
によつて、上記の場合とまつたく同様な効果が得
られる。
Similarly, in a charge-coupled device having a multi-channel structure, one input gate electrode of the charge input section is divided in the charge transfer direction by a number equal to the number of transfer channels, and each divided input gate electrode is By applying a direct current bias, effects similar to those in the above case can be obtained.

以上説明したように本発明によれば、転送チヤ
ネルごとに適切なバイアス電荷を注入することに
よつて、各転送チヤネルでの暗電流、転送効率の
違いによつて生じる出力電圧のばらつきや、出力
部での結合容量の違いによつて生じる出力電圧の
ばらつきが補正できるような複数チヤネル型電荷
結合素子が得られる。
As explained above, according to the present invention, by injecting an appropriate bias charge to each transfer channel, variations in output voltage caused by differences in dark current and transfer efficiency in each transfer channel, and output A multi-channel charge-coupled device can be obtained in which variations in output voltage caused by differences in coupling capacitance between sections can be corrected.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のデユアルチヤネル型電荷結合素
子、第2図は第1図の出力部の説明図、第3図は
第1図のデユアルチヤネル型電荷結合素子に印加
される転送パルスとその出力波形、第4図は本発
明をデユアルチヤネル型電荷結合素子に応用した
一実施例を示すための図、第5図は第4図の入力
ゲート電極に印加される直流バイアスと転送チヤ
ネルに注入される電荷量の関係を説明するための
図、第6図は第4図のデユアルチヤネル型電荷結
合素子の出力信号波形、第7図は第4図の他の実
施例を説明するための図、第8図は本発明を三列
転送チヤネル型電荷結合素子に応用した例を示す
ための図である。図において、 11……インプツトダイオード、12,13,
41a,41b,71a,71b,81a,81
b,81c……入力ゲート電極、14……スイツ
チングゲート電極、15……浮遊拡散層、16…
…出力アンプ、17……転送チヤネルAの第1電
極、18……転送チヤネルBの第1電極、21…
…転送チヤネルAの最終電極、22……転送チヤ
ネルBの最終電極、23……出力端子、42……
チヤネルストツパー、43……電圧源、44,8
3a,83b,83c……可変抵抗、45,46
……入力ゲート電極13下の電荷蓄積領域、82
……転送チヤネルCの第1電極、φ1,φ2,φ3
…転送パルス、C1,C2,C3,C1′,C2′,C3′……
結合容量。
Figure 1 is a conventional dual channel charge coupled device, Figure 2 is an explanatory diagram of the output section in Figure 1, and Figure 3 is a transfer pulse applied to the dual channel charge coupled device in Figure 1 and its output. FIG. 4 is a diagram showing an embodiment in which the present invention is applied to a dual-channel charge-coupled device, and FIG. 5 shows the waveforms of the DC bias applied to the input gate electrode of FIG. 4 and the waveforms injected into the transfer channel. 6 is a diagram for explaining the relationship between the amount of charge, FIG. 6 is an output signal waveform of the dual channel charge coupled device of FIG. 4, FIG. 7 is a diagram for explaining another embodiment of FIG. 4, FIG. 8 is a diagram showing an example in which the present invention is applied to a three-row transfer channel type charge coupled device. In the figure, 11...input diode, 12, 13,
41a, 41b, 71a, 71b, 81a, 81
b, 81c... Input gate electrode, 14... Switching gate electrode, 15... Floating diffusion layer, 16...
...Output amplifier, 17...First electrode of transfer channel A, 18...First electrode of transfer channel B, 21...
...Final electrode of transfer channel A, 22...Final electrode of transfer channel B, 23...Output terminal, 42...
Channel stopper, 43... Voltage source, 44, 8
3a, 83b, 83c...variable resistor, 45, 46
...Charge storage region under the input gate electrode 13, 82
...First electrode of transfer channel C, φ 1 , φ 2 , φ 3 ...
…Transfer pulse, C 1 , C 2 , C 3 , C 1 ′, C 2 ′, C 3 ′...
Coupling capacity.

Claims (1)

【特許請求の範囲】[Claims] 1 インプツトダイオードと第1および第2の入
力ゲート電極とスイツチングゲート電極とで構成
された電荷入力部と、該電荷入力部からの信号電
荷を複数列に分けてそれぞれ位相の異なる転送パ
ルスで転送する電荷転送チヤネルと、該複数列の
電荷転送チヤネルからの信号電荷を合成出力する
電荷出力部とを有する電荷結合素子において、前
記第1および第2の入力ゲート電極のうちいずれ
か一方を前記複数列の電荷転送チヤネルのそれぞ
れに対応して独立な電気信号が印加されるように
分割し、これら分割された入力ゲート電極のそれ
ぞれに前記複数列の電荷転送チヤネルからの信号
出力電圧のばらつきが補正されるようなそれぞれ
異なる直流バイアス電圧を印加することを特徴と
する電荷結合素子。
1 A charge input section composed of an input diode, first and second input gate electrodes, and a switching gate electrode, and a signal charge from the charge input section is divided into multiple columns and transferred with transfer pulses having different phases. In a charge-coupled device having a charge transfer channel for transferring and a charge output section for combining and outputting signal charges from the plurality of columns of charge transfer channels, one of the first and second input gate electrodes is connected to the charge transfer channel. It is divided so that independent electric signals are applied to each of the plurality of rows of charge transfer channels, and variations in signal output voltage from the plurality of rows of charge transfer channels are applied to each of these divided input gate electrodes. A charge-coupled device characterized by applying different DC bias voltages that are corrected.
JP10353378A 1978-08-24 1978-08-24 Charge coupld element Granted JPS5529191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10353378A JPS5529191A (en) 1978-08-24 1978-08-24 Charge coupld element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10353378A JPS5529191A (en) 1978-08-24 1978-08-24 Charge coupld element

Publications (2)

Publication Number Publication Date
JPS5529191A JPS5529191A (en) 1980-03-01
JPS6316910B2 true JPS6316910B2 (en) 1988-04-11

Family

ID=14356502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10353378A Granted JPS5529191A (en) 1978-08-24 1978-08-24 Charge coupld element

Country Status (1)

Country Link
JP (1) JPS5529191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293214A (en) * 1988-05-20 1989-11-27 Kayaba Ind Co Ltd Attitude control device
JPH0456504U (en) * 1990-09-21 1992-05-14

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5345182A (en) * 1976-10-05 1978-04-22 Matsushita Electric Ind Co Ltd Semiconductor device
JPS5371578A (en) * 1976-12-08 1978-06-26 Western Electric Co Charge transfer device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5345182A (en) * 1976-10-05 1978-04-22 Matsushita Electric Ind Co Ltd Semiconductor device
JPS5371578A (en) * 1976-12-08 1978-06-26 Western Electric Co Charge transfer device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293214A (en) * 1988-05-20 1989-11-27 Kayaba Ind Co Ltd Attitude control device
JPH0456504U (en) * 1990-09-21 1992-05-14

Also Published As

Publication number Publication date
JPS5529191A (en) 1980-03-01

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