JPH04369187A - Ccd solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve a charge-voltage conversion efficiency for a floating diffusion layer, to enhance the sensitivity of the CCD solid-state image pickup element and to improve the S/N by reducing a parasitic capacitance between the floating diffusion and an output gate. CONSTITUTION:This solid-state image pickup element is provided with an output section 1, in which a signal charge from a final stage of a charge transfer section 2 comprising a CCD is once stored in a floating diffusion FD via an output gate OG and a voltage change V based on the stored charge is fed to a source follower circuit 5 and an image pickup signal S is extracted from an output terminal phiout of the source follower circuit 5. The output of the source follower circuit 5 and the output gate OG are connected to feed back the image pickup signal S outputted from the source follower circuit 5 to the output gate OG.

Description

Detailed Description of the Invention [0001] [Industrial Application Field] The present invention relates to a CCD solid-state image sensor,
In particular, the present invention relates to a CCD solid-state image sensor having a so-called floating diffusion amplifier that converts signal charges from a charge transfer section configured with a CCD into an output voltage. 2. Description of the Related Art As shown in FIG. 4, a conventional CCD solid-state image pickup device, particularly its output section, is a floating charge transfer section 21 formed of a CCD, with an output gate OG in between. A discharging element 22 consisting of a diffusion FD, a reset gate PG, and a drain region D, and further downstream of this discharging element 22 an output element Q1 and a load resistance element Q.
The source follower circuit 23 includes a source follower circuit 23 consisting of 2 parts. In the charge transfer section 21, the signal charge transferred from below the transfer electrode TG at the final stage is temporarily accumulated in the floating diffusion FD, and the voltage change ΔV based on the accumulated charge is transferred to the source follower circuit at the subsequent stage. 23, it is taken out as an output voltage (imaging signal) S from the output terminal φout of the source follower circuit 23. Output terminal φou of source follower circuit 23
After taking out the imaging signal S from t, the reset gate P
Floating by supplying reset pulse φPG to
Reset the diffusion FD to the initial voltage Vdd,
The charges accumulated in the floating diffusion FD are swept out to the drain region D side. [0005] Generally, the charge-voltage conversion efficiency η in a floating diffusion FD is expressed by the following equation 1. [Equation 1] η=ΔV/ΔQ=1/CFD Here, ΔV represents a voltage change based on the amount of signal charge ΔQ accumulated in the floating diffusion FD. Further, CFD is the total capacitance related to the floating diffusion, and this total capacitance CFD is expressed by the following equation. CFD=CB +COG+CPG+CL+CM 00
[07] Here, each capacitance is as shown in FIG. 5. CB is the capacitance between the floating diffusion FD and the substrate or adjacent channel, COG is the capacitance between the floating diffusion FD and the output gate OG, and CPG is the floating diffusion capacitance. FD and reset gate P
CL is the wiring capacitance, and CM is the capacitance in the source follower circuit 23. As can be seen from Equation 1 above, the charge-voltage conversion efficiency η of the floating diffusion FD can be increased by reducing the total capacitance CFD of the floating diffusion FD. Conventionally, methods such as reducing the area of the floating diffusion FD have been used to achieve this, but in the conventional CCD solid-state image sensor, the potential Vog applied to the output gate OG is a fixed potential. Therefore, floating diffusion F
The parasitic capacitance COG between D and the output gate OG cannot be reduced, which is an obstacle to improving the charge-voltage conversion efficiency η. [0010] This also applies to a floating gate output type CCD solid-state imaging device that can detect signal charges non-destructively. [0011] The present invention was made in view of the above problems, and its purpose is to reduce the parasitic capacitance between the floating diffusion and the output gate, and to improve the charge-voltage conversion efficiency in the floating diffusion. It is an object of the present invention to provide a CCD solid-state image sensor that can improve the sensitivity and S/N ratio of the CCD solid-state image sensor. [Means for Solving the Problems] The present invention stores signal charges from the final stage of a charge transfer unit 2 composed of a CCD in a floating diffusion FD via an output gate OG, and In a CCD solid-state image sensing device having an output section 1, in which a voltage change ΔV based on the charge is supplied to an output amplifier 5, an image signal S is taken out from an output terminal φout of the output amplifier 5, and the output from the output amplifier 5 is Output gate OG (imaging signal S)
Return to and configure. [Operation] According to the configuration of the present invention described above, the output gate OG
Since the imaging signal S that is in phase with the voltage change ΔV in the floating diffusion FD is supplied to the floating diffusion FD, the parasitic capacitance COG between the floating diffusion FD and the output gate OG is reduced. In reality, if the gain of the output amplifier 5 is G, it can be reduced by a factor of (1-G). As a result, the total capacitance CFD of the floating diffusion FD can be reduced, and the charge-voltage conversion efficiency η of the floating diffusion FD can be improved. This leads to improved sensitivity and improved S/N ratio of the CCD solid-state image sensor. [Embodiments] Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is an equivalent circuit diagram schematically showing the configuration of the CCD solid-state image sensor according to this embodiment, particularly the output section 1 thereof. [0015] The output section 1 of this CCD solid-state image sensor is
It has a so-called FDA (floating diffusion amplifier) 3 that converts signal charges from a charge transfer section 2 composed of a CD into an output voltage. That is, at the next stage of the charge transfer section 2, there is a discharging element 4 consisting of a floating diffusion FD, a reset gate PG, and a drain region D across the output gate OG, and further this discharging element 4
At the next stage, there is at least an output element Q1 and a load resistance element Q.
The source follower circuit 5 includes a source follower circuit 5 consisting of 2 parts. The output element Q1 and the load resistance element Q2 are constructed of, for example, an N-channel type MOSFET (MOS type field effect transistor). The charge transfer section 2 includes, for example, a horizontal resistor 7 composed of an N-type impurity diffusion region band on the surface of a P-type silicon substrate 6, and a horizontal resistor 7 formed on the horizontal resistor 7 with an insulating film 8 interposed therebetween. It has first and second horizontal transfer electrodes 9 and 10 made of first and second polycrystalline silicon layers, and furthermore, these two horizontal transfer electrodes 9 and 10 form a set and are sequentially horizontally transferred. It is arranged and formed in the direction. Then, two-phase driving pulses φ1 and φ having opposite phases to each other are generated.
2 is applied to each set, the signal charges are sequentially transferred to the output section 1 side. In the charge transfer section 2, the signal charge transferred from the transfer electrode 9 at the final stage is temporarily stored in the floating diffusion FD, and the voltage change ΔV based on the accumulated charge is transferred to the source follower circuit 5 at the subsequent stage. By supplying the signal to the output terminal φout of the source follower circuit 5, an output signal (imaging signal) S is taken out. After taking out the output signal S from the output terminal φout, a reset pulse φPG is applied to the reset gate PG.
By supplying , the floating diffusion FD is reset to the initial voltage Vdd, and the signal charges accumulated in the floating diffusion FD are swept out to the drain region D side. In addition, the two-phase drive pulse φ
1 and φ2 and the output timing of the reset pulse φPG are shown in FIG. Therefore, the voltage change ΔV from the floating diffusion FD becomes a signal containing a signal component based on the precharge drain voltage Vdd and the amount of accumulated charge, as shown in waveform (2) in FIG. In addition, the output signal S from the source follower circuit 5 has a voltage change ΔV from the floating diffusion FD, as shown in the waveform ■, assuming that the gain of the source follower circuit 5 is G (0.7<G≦1). The signal is multiplied by G, and the relationship between each signal (voltage change ΔV and output signal S) is in phase. At this time, in the output signal S from the source follower circuit 5, the potential corresponding to the precharged drain voltage Vdd in the voltage change ΔV from the floating diffusion FD is Vo, and the magnitude relationship is determined by the source follower circuit 5. From the relationship of gain G, Vdd
<Vo. In this example, the output side of the source follower circuit 5 and the output gate OG are connected, and the output signal (imaging signal) output from the source follower circuit 5 is
S is fed back to the output gate OG. In this case, since the output gate OG is supplied with a signal that is in phase with the voltage change ΔV in the floating diffusion FD, the floating diffusion FD and the output gate OG
The parasitic capacitance COG between the two is reduced. In reality, if the gain of the source follower circuit 5 is G, the parasitic capacitance COG can be reduced by a factor of (1-G). From this, ideally,
By changing the bias potential Vgg applied to the gate of the load resistance element Q2 of the source follower circuit 5, the gain G of the source follower circuit 5 is brought close to 1, and the voltage change Δ from the floating diffusion FD is
By making the potential difference (for example, Vdd-Vo) between V and the output signal S from the source follower circuit 5 close to 0, the parasitic capacitance COG between the floating diffusion FD and the output gate OG can be equivalently reduced to 0. can do. As described above, according to this example, the output from the source follower circuit 5 (imaging signal S) is sent to the output gate OG.
Since the configuration is such that the parasitic capacitance COG between the floating diffusion FD and the output gate OG can be reduced, the total capacitance CFD related to the floating diffusion FD can be reduced. be able to. From this, it is possible to improve the charge-voltage conversion efficiency η in the floating diffusion FD, and it is possible to improve the sensitivity and S/N ratio of the CCD solid-state image sensor. In the above embodiment, the voltage change ΔV from the floating diffusion FD is output to the output element Q1.
Although an example has been shown in which the output section 1 is amplified by the source follower circuit 5 consisting of the load resistance element Q2 and the source follower circuit 5, the application is applicable not only to the source follower circuit 5 but also to any voltage follower type amplifier. . In the above embodiment, the floating charger is used as a voltage converter for the signal charge from the charge transfer section 2.
Although a diffusion FD is used, the present invention is applicable not only to this floating diffusion FD but also to a floating gate output type CCD solid-state image sensor. In this case, the charge-voltage conversion efficiency η is different from Equation 1 above, but by reducing the parasitic capacitance, the charge-voltage conversion efficiency η is
A high voltage conversion efficiency η is achieved. Furthermore, in the above embodiment, by using N type as the impurity diffusion region constituting the charge transfer section 2,
Although the case where the carriers handled as signal charges are electrons is shown, it is also applicable to the case where the impurity diffusion region constituting the charge transfer section 2 is of P type and the carriers handled as signal charges are holes. . [0027] According to the CCD solid-state imaging device according to the present invention, the parasitic capacitance between the floating diffusion and the output gate can be reduced.
It is possible to improve the charge-voltage conversion efficiency in diffusion, and also to improve the sensitivity and S/N ratio of the CCD solid-state image sensor.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing the configuration of an output section of a CCD solid-state image sensor according to the present embodiment.

FIG. 2 is a waveform diagram showing output timings of two-phase drive pulses and reset pulses.

FIG. 3 is a waveform diagram showing the relationship between voltage changes from the floating diffusion and output signals from the source follower circuit.

FIG. 4 is an equivalent circuit diagram showing the configuration of an output section of a conventional CCD solid-state image sensor.

FIG. 5 is an equivalent circuit diagram showing the total capacitance related to floating diffusion.

[Explanation of symbols]

1 Output section 2 Charge transfer section 3 FDA 4 Discharge element 5 Source follower circuit OG Output gate FD Floating diffusion PG Reset gate D Drain region

Claims (1)

[Claims] Claim 1: By temporarily accumulating the signal charge from the final stage of the charge transfer section composed of a CCD in a floating diffusion via an output gate, and supplying a voltage change based on the accumulated charge to an output amplifier, A CCD solid-state image sensor having an output section configured to output an image signal from an output terminal of the output amplifier, wherein the output from the output amplifier is fed back to the output gate.