JPS5534352A - Sample hold circuit - Google Patents

Sample hold circuit

Info

Publication number
JPS5534352A
JPS5534352A JP10684678A JP10684678A JPS5534352A JP S5534352 A JPS5534352 A JP S5534352A JP 10684678 A JP10684678 A JP 10684678A JP 10684678 A JP10684678 A JP 10684678A JP S5534352 A JPS5534352 A JP S5534352A
Authority
JP
Japan
Prior art keywords
circuit
sample hold
hold circuit
windings
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10684678A
Other languages
Japanese (ja)
Inventor
Teruo Imamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP10684678A priority Critical patent/JPS5534352A/en
Publication of JPS5534352A publication Critical patent/JPS5534352A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electronic Switches (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To carry out a precise sampling by adding the level shift circuit to the floating type analogue switch using sample hold circuit.
CONSTITUTION: To the sample hold circuit, the level shift circuit comprising the fixed voltage generating circuits V1, V2 and impedance converters 51, 52. The switching signal supply source 3 is formed by the pulse transformer having three windings. The windings 42 and 43 are formed so as to excite the reverse direction voltage to each other. In the construction as mentioned above, when input signal is impressed to the terminal 11 of the analogue switch 1, respectively the negative side level shifted input signal is put out to output of the circuit 5 and the positive side level shifted signal is put out as output and the error discharge of the hold capacitor 2 is prevented. Since the amplitude of the pulse of the switching signal of the switch is constant, error in the switching time is not found and the precise sampling can be done.
COPYRIGHT: (C)1980,JPO&Japio
JP10684678A 1978-08-31 1978-08-31 Sample hold circuit Pending JPS5534352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10684678A JPS5534352A (en) 1978-08-31 1978-08-31 Sample hold circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10684678A JPS5534352A (en) 1978-08-31 1978-08-31 Sample hold circuit

Publications (1)

Publication Number Publication Date
JPS5534352A true JPS5534352A (en) 1980-03-10

Family

ID=14444007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10684678A Pending JPS5534352A (en) 1978-08-31 1978-08-31 Sample hold circuit

Country Status (1)

Country Link
JP (1) JPS5534352A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212697A (en) * 1988-06-30 1990-01-17 Yokogawa Electric Corp Sample and hold circuit
JPH0991987A (en) * 1995-09-27 1997-04-04 Nec Corp Sample hold circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0212697A (en) * 1988-06-30 1990-01-17 Yokogawa Electric Corp Sample and hold circuit
JPH073753B2 (en) * 1988-06-30 1995-01-18 横河電機株式会社 Sample hold circuit
JPH0991987A (en) * 1995-09-27 1997-04-04 Nec Corp Sample hold circuit

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