JPH073999B2 - Sync pulse generator circuit synchronized with video sync signal - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to various types of sampling in a video digitizing system for converting an analog video signal into a digital signal, performing various kinds of signal processing, and again converting the analog video signal into a screen display for screen display. The present invention relates to a frequency synchronizing pulse generating circuit.

(Prior art and its problems) In a device that converts an analog video signal into a digital signal, converts the analog signal again by changing a scanning frequency by digital signal processing, and displays a video with different screen sizes, digital signal processing is performed. To do this, various sync pulses with different sampling frequencies are required.

FIG. 3 is a block diagram showing a conventional configuration example of a synchronizing pulse generating circuit for various sampling frequencies by a frequency synthesizer using a PLL (phase locked loop). In the figure, 1 is a phase comparator (PC) that detects a two-input phase or frequency difference, 2 is a low-pass filter (LPF) that integrates the phase difference to obtain a direct current, and 3 is an oscillation frequency with a direct current voltage or current. A variable voltage controlled oscillator (VCO) 4 is a programmable divider that provides a reference signal Fv to the phase comparator 1. This is also called an arbitrary decimal divider, and the division ratio can be arbitrarily set according to the change of the built-in program, and K is an arbitrary decimal division ratio. 5,6,7 are all dividers with a division ratio of 2,
N (n: 1, 2, 3 ... Arbitrary) are connected in series so that the output frequency F ₀ is divided by a factor of 2 in order to obtain sync pulse outputs for various sampling frequencies.

Now, assuming the repetition frequency Fr of the video sync signal as the reference frequency, the output frequency F when the loop is completely locked
_{For 0} , F ₀ = K · Fr. Also, the n output frequencies of the frequency dividers 5 to 7 are respectively And the frequency step Can be set to.

However, this circuit has a drawback that the phase of the divided output pulse is unstable with respect to the phase of the output frequency F ₀ . That is, since the frequency dividers 5, 6, and 7 are not synchronized with the video synchronization signal Fr, the output of each frequency divider, that is, 1/2,
The output after dividing to 1/4, ... 1 / 2n may be out of phase when the power is turned on. This is shown in the timing chart at points a, b and c in FIG.

That is, paying attention to the output waveform of the VCO 3 in FIG. 3 and the output waveform of the frequency divider 5 after being divided by 1/2 (point b), the phase is changed to a waveform with respect to the waveform when the power is turned on. 18
Waveforms different by 0 ° may occur, and the output (point c) of the frequency divider 6 that performs 1/2 division is a waveform when it is a waveform and a waveform when it is a waveform. Waveforms that are 180 degrees out of phase with each other may occur.
After all, at the point c, one of four kinds of waveforms having a phase difference of 0 °, 90 °, 180 °, 270 ° is generated. Therefore, any of the 2n (however, n: 1, 2, ...) Waveforms are generated in the output of the last frequency divider 7, and it is always possible to obtain an output waveform with no phase shift each time the power is turned on. It has the drawback of being difficult and unstable.

Further, as another example of the conventional synchronizing pulse generating circuit, there is a circuit shown in the block diagram of FIG. This circuit
This is a circuit in which frequency dividers 5 to 7 and a programmable divider 64 having a frequency division ratio K '= 2n / K are inserted in a feedback loop to the phase comparator 1. In this circuit, a sampling clock synchronized with the frequency Fr of the input synchronizing video signal is obtained, but the frequency division ratio K ′ of the programmable divider 64 is arbitrarily changed to output the output frequency F _{0 with} respect to the frequency Fr of the input synchronizing video signal. The frequency variable step width when changing
If the number of frequency dividers 5 to 7 increases, there is a drawback that the step width becomes even larger.

(Object of the Invention) An object of the present invention is to solve the above-mentioned problems and to provide a synchronization for a sampling clock in which the phase of each pulse output divided at the time of power-on is always stable and the frequency interval can be finely set. It is to provide a pulse generation circuit.

(Structure and Operation of the Invention) The synchronizing pulse generating circuit according to the present invention divides the output of the voltage controlled oscillator by the programmable divider at an arbitrary dividing ratio and returns the phase difference between the reference signal and the input video synchronizing signal. In a synchronous pulse generator using a phase-locked loop (PLL) for detecting and controlling the voltage controlled oscillator so that the detected output becomes zero by the detected output, the output of the voltage controlled oscillator is serially connected in series. It is characterized in that a sampling synchronizing pulse synchronized with the video synchronizing signal is obtained at each output of the plurality of 1/2 frequency dividers reset by the video synchronizing signal.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of the present invention. In the figure, the names and numbers of the respective parts constituting the circuit are the same as in FIG. The present invention is characterized in that the input video synchronizing signal is applied to the frequency dividers 5, 6, and 7 having the frequency division ratio of 2 to reset the frequency dividers 5 to 7 with the video synchronizing signal Fr.

FIG. 2 shows a programmable divider 4 of the circuit shown in FIG.
9 is a timing chart showing waveforms of respective parts when the frequency division ratio K of is operated to be 12, for example. In the figure, the waveform is a video synchronizing signal, and only the video synchronizing signal is extracted from the entire video signal shown in FIG. The waveform is the waveform of the output A point of VCO3, and the waveform is divided by 1/2 by the frequency divider 5 and then B
It is a waveform of dots. Further, FIG. 5 is a time chart of the entire video signal.

Since the frequency dividers 5 to 7 are reset by the video synchronization signal Fr and the output signal after frequency division is forcibly set to the LOW level, after reset is released, the input signal rises at a constant phase. Be sure to stand up. At this time, the output of the frequency divider is
Since it is reset by the video sync signal Fr, the video sync signal Fr
After that, the frequency division output, that is, the sampling clock is not generated for a while. For example, as shown in the waveform, an interval of 2 pulses is generated. However, as shown in FIG. 5, there is a back porch after the video sync signal is generated, and video data is not generated for a while, so even if there is no sampling clock for a while after the video sync signal is generated (during the back porch). There is no problem.

Next, the variable step width of the output frequency F _{0 at} the point A will be explained by comparing that the circuit of the present invention is superior to the case of the conventional circuit shown in FIG.

The output frequency F _{0 at} point A in FIG. 1 is expressed by the following equation as described above.

F ₀ = K · Fr On the other hand, the output frequency F _{0 at} point A ′ in FIG. 6 is given by the following equation.

F ₀ = K ′ · 2nFr From the above two equations, the frequency division ratio K ′ of the programmable divider 64 in FIG. 6 can be expressed by the frequency division ratio K of the programmable divider 4 in FIG.

Since the frequency division ratios of the programmable dividers 4 and 64 are both arbitrary numbers (1, 2, 3, ...), changing the frequency division ratio of the programmable dividers 4 and 64 by 1 changes the output frequency F _{0 at} point A by Fr. On the other hand, A ′ in FIG.
The output frequency F _{0 at the} point changes by 2nFr. In other words, the programmable divider 4 of the circuit of the present invention.
It can be seen that in the conventional circuit, 1 division is 2n times as large as the division ratio of 1 division.

Therefore, in the conventional circuit of FIG. 6, when the number of frequency dividers n increases, the variable step width of the output frequency F ₀ becomes larger, whereas in the circuit of the present invention, the number of frequency dividers increases. There is an effect that F ₀ can be set with a constant variable step width.

As a specific example, the input frequency Fr = 1 kHz, the number of frequency dividers n = 2
Since the values of the frequency division ratios K and K'of the programmable dividers 4 and 64 are arbitrary numbers (1,2,3 ...), the output frequency F ₀ in the circuit of the present invention (FIG. 1) is From the above formula F ₀ = K · Fr, if K = 1: F ₀ = 1 × 1000 = 1000 (Hz) If K = 2: F ₀ = 2 × 1000 = 2000 (Hz) K = 3 Case: F ₀ = 3 × 1000 = 3000 (Hz), which can be set with a step width of 1000 Hz. On the other hand, in the conventional circuit (FIG. 6), from F ₀ = K ′ × 2n × Fr = K ′ × 4 × Fr, if K ′ = 1: F ₀ = 1 × 4 × 1000 = 4000 (Hz) K When ′ = 2: F ₀ = 2 × 4 × 1000 = 8000 (Hz) When K ′ = 3: F ₀ = 3 × 4 × 1000 = 12000 (Hz), which can be set only with a step width of 4000 Hz.

In the above example, it is clear that the circuit of the present invention is advantageous as the number of frequency dividers having a frequency division ratio of 2 increases, though the step width becomes larger, although this is a difference of this degree.

(Effects of the Invention) As described in detail above, by carrying out the present invention, the output frequency can be set with a frequency variable step width that is not affected by the number of frequency dividers. There is an advantage that there is no phase shift of the output sampling clock of the frequency divider and the sampling clock always synchronized with the video synchronizing signal can be surely created.

Supplying a stable sampling clock by the circuit of the present invention is to ensure stable operation of the entire apparatus that performs digital processing, and its practical effect is extremely large.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of the present invention, FIG. 2 is a timing chart of each point of the circuit of FIG. 1, FIG. 3 is a block diagram showing an example of a conventional circuit, and FIG. 5 is a timing chart of each point of the circuit shown in FIG. 5, FIG. 5 is a time chart of an input signal, and FIG. 6 is a block diagram of a circuit showing another example of the related art. 1 ... Phase comparator (PC), 2 ... Low-pass filter (LP
F), 3 ... Voltage controlled oscillator (VCO), 4, 64 ... Programmable divider, 5-7 ... Divider with a division ratio of 2.

Claims (1)

[Claims] 1. A phase difference between a reference signal fed back after frequency division of an output of a voltage controlled oscillator by a programmable divider at an arbitrary frequency division ratio and an input video synchronizing signal is detected, and the detected output outputs the voltage controlled oscillator. In a synchronization pulse generator using a phase locked loop (PLL) for controlling the detection output to be zero, a plurality of 1 / s that are sequentially connected to the output of the voltage controlled oscillator and reset by the video synchronization signal A synchronizing pulse generating circuit synchronized with a video synchronizing signal, characterized in that a sampling synchronizing pulse synchronized with the video synchronizing signal is obtained at each output of the frequency divider.