JP3193535B2 - Sampling clock generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock generation circuit, and more particularly, to a method for converting an input signal to an A signal.
When digital conversion is performed by the / D converter, n
Generate a sampling clock having a frequency twice as high as A
The present invention relates to a sampling clock generation circuit provided to a / D converter.

[0002]

2. Description of the Related Art An example of a conventional apparatus is shown in FIG. The sampling clock generation circuit 1 includes, for example, a low-pass filter 2
And a waveform shaper 3 and a PLL circuit 4. The low-pass filter 2 removes a noise component having a frequency twice or more contained in the input signal and the like, and prevents the occurrence of a folding error at the time of A / D conversion. The waveform shaper 3 is composed of, for example, a zero cross comparator, and shapes a sine wave input signal applied from the low-pass filter 2 into a square wave having a duty ratio of 50%.

The PLL circuit 4 divides the free-running oscillation frequency of an oscillator (not shown) by 1 / n, and adjusts the oscillation frequency so that the divided signal synchronizes with the square wave signal input from the waveform shaper 3 in phase. Control. When the phases are synchronized, the oscillation frequency of the PLL circuit 4 becomes n times the frequency of the input signal, and this signal is supplied to the A / D converter 5 as a sampling clock. The A / D converter 5 converts the input signal into a digital signal at the timing of the clock and sends the data to the signal processing unit 6. The signal processing unit 6 performs processing specified for the device on the input data.

[0004]

The above conventional sampling clock generation circuit has a relatively simple structure.
Operation is also reliable for normal input signals. But,
When a DC component or the like is superimposed on the input signal, inconvenience occurs.

FIG. 4 shows an example. FIG. 4A illustrates an example in which a noise voltage and a positive DC voltage are superimposed on an input signal, for example. When such a signal is applied to the filter 2, the noise voltage having a relatively high frequency is removed but the DC voltage cannot be removed, and the output waveform of the filter 2 is as shown in (b) of FIG. become. Therefore, the output waveform of the waveform shaper 3 is a square wave with an unbalanced duty ratio, for example, as shown in FIG.

In this case, the output waveform of the oscillator in the PLL circuit 4 generally has a duty ratio of approximately 50%, so that the phase of the signal waveform obtained by dividing the frequency by 1 / n is the waveform of (c). When trying to synchronize (lock-in) to the phase of, the synchronization may become unstable or impossible depending on the degree of imbalance in the duty ratio. In the case where synchronization is not possible, as shown in (d) of FIG. 4A, a signal obtained by dividing the free-running oscillation frequency of the oscillator by 1 / n is used as the sampling clock, and thus becomes independent of the frequency of the input signal. .

FIG. 4B shows an example in which the level of the input signal is smaller than the positive DC voltage superimposed on the input signal. In this example, the zero-cross comparator waveform shaper 3 will shake off the positive side as shown in (c) of FIG. 4 (B), a synchronization impossible. Therefore, the PLL circuit 4 does not operate normally, and the sampling clock is fixed at the H level (or the L level indicated by the broken line) as shown in FIG. 4B, and the sampling is stopped.

When the sampling clock becomes a signal of 1 / n of the free-running oscillation frequency as described above, for example, for an input signal having a relatively low frequency, the number of sampling data in one wave period increases, so that the memory of the signal processing section is Overflows, and the number of sampling data in one wave period may be insufficient for an input signal having a relatively high frequency. Further, if the sampling is stopped, sampling cannot be performed naturally.

[0009] Whether or not a DC voltage is superimposed on a signal to be input to the apparatus and its magnitude generally depend on the state of the signal supply source. Therefore, in order to avoid the above problem, it is necessary to check the presence or absence of the DC voltage on the device side by other means each time, but it is extremely troublesome.

The present invention has been made in view of the above circumstances, and has as its object to eliminate the need to check the presence or absence of a DC voltage, to obtain a sampling clock that is always proportional to n times the frequency of an input signal. Another object of the present invention is to provide a sampling clock generation circuit capable of checking the presence or absence of a DC voltage as required.

[0011]

As described above, the DC voltage superimposed on the input signal is an unnecessary component for generating the sampling clock. Therefore, in the present invention, a high-pass filter for removing a DC component is provided in a stage preceding the low-pass filter, and an input side of the low-pass filter is provided.
The gist of the present invention is to provide a changeover switch for applying either the AC signal sent from the high-pass filter or the AC input signal input to the high-pass filter to the low-pass filter.

By applying the AC input signal to the low-pass filter through the high-pass filter, the DC voltage superimposed on the AC input signal is removed, and the voltage output from the waveform shaper becomes a square wave signal with a duty ratio of 50%. Therefore, in the PLL circuit, the phase cycle of the 1 / n frequency-divided signal of the oscillation frequency and the square wave signal becomes possible,
A sampling clock having a frequency n times as high as the input signal is obtained from the circuit.

When it is unclear whether a DC voltage is superimposed on an input signal, A / D conversion data obtained when an AC input signal is passed through a high-pass filter and a direct low-pass signal without passing the AC input signal through a high-pass filter. By comparing the A / D converted data when applied to the filter and checking whether or not both data are the same, it is possible to determine the presence or absence of a DC voltage.

[0014]

FIG. 1 shows an embodiment of the present invention.
In the figure, a sampling clock generation circuit 1a
For example, a high-pass filter 2a for removing a DC voltage superimposed on an input signal, a low-pass filter 2, a waveform shaper 3, and a P
And an LL circuit 4.

In this case, a switch S is provided on the input side of the low-pass filter 2. When the switch S is connected to the contact a, the output of the high-pass filter 2a is applied to the low-pass filter 2 and the switch S is connected to the contact b. When connected to the side, the input signal is directly applied to the low-pass filter.

The operation of each unit when the switch S is connected to the contact a will now be described with reference to FIG. FIG. 2A shows a waveform of an input signal on which, for example, a positive DC voltage is superimposed. When this input signal is applied to the high-pass filter 2a, the output thereof becomes a DC voltage component as shown in FIG. Is removed from the waveform. The output of the high-pass filter 2a is applied to the low-pass filter 2 at the next stage, where the noise component is removed as shown in FIG.

The waveform shaper 3 includes the low-pass filter 2
Is shaped into a square wave with a duty ratio of 50% by a zero-cross comparator, and output to the PLL circuit 4. This output waveform is shown in FIG.

The PLL circuit 4 sets the phase of the square wave signal applied from the waveform shaper 3 and the oscillation frequency of the internal oscillator to 1 / n.
The oscillation frequency is controlled so that the phase of the 1 / n frequency-divided signal is synchronized with the phase of the square wave signal. In the phase locked state, the fundamental frequency of the 1 / n frequency-divided signal matches the fundamental frequency of the square wave signal, that is, the frequency of the input signal. FIG. 2 (e) shows the 1 / n frequency-divided signal at this time, and FIG. 2 (f) shows the oscillation signal of the internal oscillator having n times the frequency of the frequency-divided signal. The signal shown in FIG. 2F is used as a sampling clock of the A / D converter 5.

On the other hand, when the switch S is connected to the contact b, the configuration becomes the same as that of the conventional sampling clock generating circuit 1 shown in FIG. And the data connected to the contact b and sampled are collected in the signal processing unit 6, and it is determined whether or not both data are the same, so that the presence or absence of a DC voltage can be determined.

[0020]

As described above, according to the sampling clock generation circuit of the present invention, even if a DC component is superimposed on an AC input signal, it is not affected by the DC component and is always n times the input signal. A sampling clock proportional to the frequency can be generated, and the configuration is relatively simple. Also, the presence or absence of a DC voltage can be checked as needed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an electrical configuration of a sampling clock generation circuit to which the present invention is applied.

FIG. 2 is a waveform diagram for explaining the operation of the sampling clock generation circuit to which the present invention is applied.

FIG. 3 is a block diagram showing an electrical configuration of a conventional device.

FIG. 4 is a waveform chart for explaining the operation of the conventional device.

[Explanation of symbols]

 1a Sampling clock generation circuit 2 Low pass filter 2a High pass filter 3 Waveform shaper 4 PLL circuit 5 A / D converter S switch

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-372226 (JP, A) JP-A-4-192788 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 1/00-1/88 H03L 7/08

Claims (1)

(57) [Claims] 1. An AC input signal that is n times as large as the signal (n ≧ n)
Generating a sampling clock having the frequency of 2),
The sampling clock generation circuit for supplying a clock the product to the A / D converter for digitally converting the AC input signal, a high pass filter for removing a DC voltage component superimposed on the signal by receiving the AC input signal, the high-pass A low-pass filter for removing a harmonic voltage component at least twice the frequency of the ac input signal from the ac signal sent by the filter and sending a fundamental wave component voltage; and the input signal sent by the low-pass filter A waveform shaper for forming a square wave voltage having a duty ratio of substantially 50% from the fundamental wave component voltage of the above, and a voltage signal obtained by dividing the oscillation frequency of the oscillator by 1 / n from the waveform shaper. together is a square wave voltage and phase synchronization are entered, the a / D converter the oscillation output of the oscillator as a sampling clock And a PLL circuit for applying to, on the input side of the low-pass filter, the high-pass
Filter or the high-pass filter
One of the AC input signals input to the
A changeover switch is added to the above low-pass filter.
Sampling clock generation circuit, characterized by being.