JPH01268390A - Imaging device - Google Patents

Abstract

PURPOSE:To reduce the fitter of a sampling start point by setting the sampling start position in one horizontal scanning by the output of an AND circuit for taking the AND of the output of a synchronizing and separating circuit and the output of a horizontal synchronizing processing circuit. CONSTITUTION:Between the output of the synchronizing and separating circuit 2 and a self-oscillating circuit, a horizontal synchronizing processing circuit 4 in which an AFC is constituted and a synchronizing signal is outputted and the AND circuit 5 for taking the AND of the output of the synchronizing and separating circuit 2 and the output of the horizontal synchronizing processing circuit 4 are provided, and the sampling start position in the one horizontal scanning line is set by the output of the AND circuit to print. Thereby, the jitter of the sampling start point of the one line is reduced to constitute a system immune from noise.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a printing apparatus that uses a video signal as an input source.

[Conventional technology]

Printing devices that use a still image composite video signal as an input source often use the following two methods: They have a frame memory (or field memory) for one screen, and store image data once in the frame memory (or field memory). There is a method in which the data is retrieved from the memory in synchronization with printing, and the still image composite video signal itself is regarded as memory, synchronized with the scanning speed of the video signal, and data sampling and printing are sequentially repeated to print one screen. It's a method.

In the latter case as well, there are two methods of data sampling: one in the vertical scanning direction and one in the horizontal scanning direction. In any case, there are two methods for determining the sampling start position in one horizontal scanning line. One method is to use the output of the synchronous separation circuit as is. In other words, from the rise (or fall) of the composite synchronization signal output from the synchronization separation circuit, the counter is operated using a tally clock that is constant with the sampling clock (or a tally clock whose frequency is an integer f&), or the starting point is determined by a monostable clock. The choice is to operate the multivibrator and decide based on its output. The other method is to determine the sampling start position based on the composite synchronization signal output from the synchronization separation circuit and the output from the oscillation circuit constituting the AFC.

[Problem to be solved by the invention]

In the conventional technology, since the starting point is the falling point (or rising point) of the composite synchronization signal in the former method, it is susceptible to noise and has a high possibility of causing malfunctions.In other words, if there is noise in the composite synchronization signal, the noise The circuit operates by regarding the generation point of the horizontal synchronization as the horizontal synchronization signal.In this case, an AFC is constructed between the synchronization separation output and the self-oscillation circuit, and its output is used as the horizontal synchronization signal and the sampling start point is set as the horizontal synchronization signal. There are many ways to decide. However, in reality, with this method, there is a jitter of about foons between the composite synchronization signal and the horizontal synchronization processing circuit output, depending on the AFC's ability, and when determining the sampling start point, the horizontal synchronization circuit output is used as the sampling clock. A normalization error exists because it must be normalized using a clock that has a constant speed (or a clock that has a frequency that is an integral multiple of that). If the sampling frequency fS is 3fsc (fsc: subcarrier) and the normalized black/y signal is fs, the normalization error will be 93ns. The effect this has on the print is, for example, when the video signal is 4M
Assuming that it is a sine curve of Hz and the number of quantization bits is 6 bits, the number of error gradations Δ is as follows: Δ = < SIN (2πX4MXΔt, ) X 3
2 (Δt: time).

If Δt=200 ns, Δ=2.8 gradation diameter will appear on the print as if a straight line in the vertical direction fluctuates in the horizontal direction.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a system configuration that has small jitter at the sampling start point of one line and is resistant to noise.

[Means to solve the problem]

The printing apparatus of the present invention includes a synchronous separation circuit that separates a composite synchronous signal from a composite video signal, and a horizontal synchronous processing circuit that configures an AFC between the output of the synchronous separation circuit and a self-oscillation circuit and outputs a horizontal synchronous signal. an AND circuit that performs a logical product of the output of the synchronization separation circuit and the output of the horizontal synchronization processing circuit; a demodulation circuit that reproduces the three primary colors from the composite video signal; and an A/D circuit that converts the output of the cover circuit into a digital signal It is characterized in that it comprises a D converter, a digital data processing section, and a printing section, and the sampling start position in one horizontal scanning line is set by the output of the AND circuit, and printing is performed.

〔Example〕

FIG. 1 shows a schematic configuration of an embodiment of the present invention.

1 is a composite video signal, 2 is a synchronization separation circuit, 3 is a demodulation circuit, 4 is a horizontal synchronization processing circuit, 5 is an AND circuit, 6 is a vertical synchronization processing circuit, 7 is a blanking processing circuit, and 8 is A/D conversion. 9 is a digital data processing section, 10 is a sampling clock generation circuit, and 11 is a printing means.

The input composite video signal 1 is turned into a composite synchronization signal (C3: polarity pressure) by the synchronization separation circuit 2.

The horizontal synchronization processing port v@4 configures AFC between the output of its own oscillation circuit and the horizontal synchronization of the composite synchronization signal output from the synchronization separation circuit 2, and generates a stable horizontal synchronization signal (H: polarity) without noise. pressure). However, this horizontal synchronizing signal H is synchronized with the horizontal synchronizing pulse of the composite synchronizing signal, includes the horizontal synchronizing pulse as shown in FIG. 2, and has the minimum pulse width. The output of the synchronization separation circuit 2 is simultaneously input to the vertical synchronization processing circuit 6 and converted into a vertical synchronization signal (2). The AND circuit 5 inputs the output signal C8 of the synchronization separation circuit 2 and the output signal H of the horizontal synchronization processing circuit 3, performs a logical product, and outputs the result (HP
: polarity negative), the output signal HP of this AND circuit 5 coincides with the horizontal synchronization pulse of the composite video signal 1, and even if there is noise on the composite video signal 1, the output signal HP of the AND circuit 5 coincides with the output of the horizontal synchronization processing circuit 4. Since it is a product, it is not output (FIG. 3). After that, the output signal HP of the AND circuit 5 is input to the blanking processing circuit 7. The operation inside the blanking processing circuit 7 will be explained below with reference to FIG. Reference numeral 41 denotes an AND circuit 5, which is composed of a NAND circuit. 42 is a blanking processing circuit 7, which includes an R-S flip-flop circuit 421, an 8-bit synchronous counter circuit 422, and an inverter circuit 4.
23. 8-bit synchronous counter 422
The clock is a clock with a constant speed and phase with the sampling clock, and the clock period of fs=3fsc is 93n.
It is s. Since the output HP of the AND circuit 41 is input to 5rWI of the R-S flip-flop 71 times 11421, when HP falls, the R-S flip-flop 71 times 142
The output (HB) of 1 changes from L to H. 5 because HB is the reset signal for the 8-bit synchronous counter 422.
The 8-bit synchronous counter 422 starts its operation from the input of the next clock. An 8-bit synchronous counter 422 is connected to the S input of the R-S flip-flop circuit 421.
The output of the most significant bit Q7 of the inverter circuit l118
423, so HB is approximately 11°92μs.
After that, it changes from H to L. HB is sampling clock 1
It is input to 0. After waiting for HB to become L, the sampling clock generation circuit 10 sends the sampling clock fs to the A/D converter 8 and starts data sampling. On the other hand, the composite video signal 1 is converted into a primary color signal by the demodulation circuit 3 and is input to the A/D converter 8.

The sampled data is processed within digital data processing.
The data is once stored in the internal memory, converted into the format of the printing means 11, read out in synchronization with the printing speed, and printed.

In this way, there will be no malfunction due to noise, and the AF
There is no sampling error due to jitter in the C circuit, and jitter can be reliably suppressed to within 1/f s. If this is substituted into the equation for Δ mentioned earlier, Δ will have '-1.3 gradations, which will approximately double the accuracy. In the present invention, the input source is a composite video signal, but RBG component signals may also be used; in this case, a demodulation circuit for the three primary colors is not required,
Since the horizontal and vertical synchronization signals are input separately, a synchronization separation circuit is not required. The RGB color signals are directly input to the A/D converter. However, if horizontal and vertical synchronization signals are mixed and input as in the EIAJ standard 21-bin multi-connector, a synchronization separation circuit is required.

〔Effect of the invention〕

As described above, according to the present invention, the jitter at the sampling start point of one line is small and a system configuration that is resistant to noise can be provided.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit configuration diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing a composite synchronization signal C8 and a horizontal synchronization signal H. FIG. 3 is a diagram showing the composite video signal, the composite synchronization signal C3, and the output HP of the AND circuit 5. FIG. 4 is a circuit diagram showing a specific configuration inside the blanking processing circuit. FIGS. 5(a) to 5(c) are schematic configuration diagrams of a conventional example. . s-1 "]- Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] A sync separation circuit that separates a composite sync signal from a composite video signal, and an AF between the output of the sync separation circuit and the self-oscillation circuit.
A horizontal synchronization processing circuit that constitutes a C (Auto Frequency Control) and outputs a horizontal synchronization signal, an AND circuit that takes an AND of the output of the synchronization separation circuit and the output of the horizontal synchronization processing circuit, and reproduces the three primary colors from the composite video signal. a demodulation circuit that converts the output of the demodulation circuit into a digital signal, an A/D converter that converts the output of the demodulation circuit into a digital signal, a digital data processing section, and a printing section, and the sampling start position in one horizontal scanning line is set by the output of the AND circuit. A printing device characterized in that it performs printing.