JPS60112388A - A/d conversion method - Google Patents

A/d conversion method

Info

Publication number
JPS60112388A
JPS60112388A JP58219448A JP21944883A JPS60112388A JP S60112388 A JPS60112388 A JP S60112388A JP 58219448 A JP58219448 A JP 58219448A JP 21944883 A JP21944883 A JP 21944883A JP S60112388 A JPS60112388 A JP S60112388A
Authority
JP
Japan
Prior art keywords
signal
signals
synchronizing
memory
picture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58219448A
Other languages
Japanese (ja)
Inventor
Naoyuki Izaki
井崎 直幸
Masayoshi Suzuki
鈴木 政善
Akio Sagawa
佐川 明男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58219448A priority Critical patent/JPS60112388A/en
Publication of JPS60112388A publication Critical patent/JPS60112388A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain A/D conversion to a single picture of one scene by synchronizing changeover timing to an R, G, and B signals of a select switch with the sampling lock of an A/D converter, and converting the R, G, and B signals into picture element signals. CONSTITUTION:A composite picture signal 1 inputted in an input terminal 10 is divided by a decoder 1 into an R component signal 2, G component signal 3 and B component signal 4, which hold color components, and these signals are inputted respectively into a select switch 3, and a line synchronizing signal 11 separated by a synchronizing separator circuit 2 is inputted into a control circuit 4. The circuit 4 generates a sampling lock signal 5 synchronized with the synchronizing signal, by which controls an A/D convertor 5, memory 6 and changeover timing of said switch 3. The picture signals R, G, and B components in line are converted into digital picture element signals and are stored in the memory 6. The circuit 4 outputs the picture element signal inside the memory 6 after synchronizing the signal with the speed of a printer 7 by a calling signal from the printer 7.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本%明はアナログ−デジタル変決方法に詠如、特に、カ
ラー画一1g号を高速に変換するに好適なアナ日グーデ
ジタル変侠方法に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an analog-to-digital conversion method, particularly to an analog-to-digital conversion method suitable for converting color image data at high speed. .

〔発明の背景〕[Background of the invention]

テレビ等Qカラー画慮をハードコピー化するだめのプリ
ンタとして、熱転写形のサーマルプリンタやイノクジエ
ツトグリ/りが66−が、これらの装置では、画一信号
であるアナログ・16号を、画素を傅成す/:)ための
デジタル信号に変換し、−・1赦・+に号とグリ/りり
走畳速度が異なるため、速成変換を行なう必要がめる。
Thermal transfer type thermal printers and inkjet printers are used as printers for making hard copies of Q color plans such as TVs, but these devices convert the analog signal No. 16, which is a uniform signal, into pixels. It is necessary to convert it into a digital signal to generate /:), and because the running speeds of -, 1, and + are different from each other, it is necessary to perform quick conversion.

前者に対しては、関連のアナログ−デジタル、(以下A
/f)と略丁)変換器が用いりn1後者のためにば、高
速データを一時記・淋し、プリンタ一連反に応じて送出
する必要yisらム己億装置(以下メモリと略り勺が用
いられる。記憶谷殖は一画面分を必要とする。
For the former, the related analog-digital, (hereinafter A
For the latter, it is necessary to temporarily store and hold high-speed data and send it to the printer in response to a series of prints. Used. Memory valley exploration requires one screen.

これらの震侯器ヤメモリVユ市販されていつ。When did these tremors become commercially available?

このような変換器fメモリを用いてカラー画慮tハード
コピー化する表置では、従来、第1図。
FIG. 1 is a conventional method for producing a color hard copy using such a converter memory.

第2図に示す方式が用いらjしている。すなわち、いま
、入力端子10に第2図中に示す複曾画像信図に示す′
Bjd号(2)、G信号(3)、B惰号(4)の包成1
に号に分けられる。これと共に同期分離回路2によって
分h11:された7レ−AltYJJ信号(6)カ、I
IJ エは、マイコンなどによって、溝底され、・16
号入出力時の各部のタイミング忙コ/トロールする制御
回路4へ入力される。制御回路4はフレーム同期信号(
6)に同期したサンプリングクロック信号を発生すると
ともに、フレーム同期信号(6)によって、A/D変換
器5、メモリ6を制御するとともに、セレクトスイッチ
3の切換タイミングを制御する。
The method shown in FIG. 2 is used. That is, the input terminal 10 is now receiving a multiple image signal ' shown in the diagram shown in FIG.
Inclusion 1 of Bjd (2), G signal (3), and B coast (4)
It is divided into numbers. At the same time, the 7-ray AltYJJ signal (6) divided h11 by the synchronization separation circuit 2, I
The IJ is processed by a microcomputer, etc., and 16
The signals are input to a control circuit 4 that controls/controls the timing of each section during signal input/output. The control circuit 4 receives a frame synchronization signal (
It generates a sampling clock signal synchronized with frame synchronization signal (6), controls the A/D converter 5 and memory 6, and controls the switching timing of the select switch 3.

いま、フレーム同期信号(6)によってセレクトスイッ
チ3が孔底分信号を選択したとき、A/D変換器5は孔
底分のアナログ画像信号を一画面(フレーム)分遵続し
てサンプルし、デジタル画素信号に変換し、メモリに記
1意する。几信号を一画面分記憶し終えると、次のフレ
ーム同期信号によってセレクトスイッチ3はG信号を選
択し、A/D変換器5は再度一画面分連続して変換する
。次いで、第三のフレーム同期信号により、セレクトス
イッチ3はB−信号を選択し、几信号、G信号と同様に
、一画面分変換されたデジタル画素信号はメモリ6内に
記1意される。このように、王画面分費して記憶された
几、G、B信号はプリンタ7の速度に合わせて順次読み
出されてハードコピー化したカラー画像を、構成してい
く。
Now, when the select switch 3 selects the hole bottom signal by the frame synchronization signal (6), the A/D converter 5 continuously samples the hole bottom analog image signal for one screen (frame), It is converted into a digital pixel signal and stored in memory. After one screen's worth of signals has been stored, the select switch 3 selects the G signal in response to the next frame synchronization signal, and the A/D converter 5 continuously converts the signal for one screen again. Next, in response to the third frame synchronization signal, the select switch 3 selects the B-signal, and the digital pixel signal converted for one screen is stored in the memory 6, similarly to the signal and the G signal. In this way, the B, G, and B signals stored in the king screen are sequentially read out in accordance with the speed of the printer 7 to form a hard copy color image.

このブロック図で1・a成される装置にではカラー画1
象1画面分を画素信号に変換するのに三フレーム分の時
間がかかシ、動画床の」最影で画面の振れが大きくなる
欠点があった。
In this block diagram, the device made in 1.a has a color image 1
It took the time of three frames to convert one screen of images into pixel signals, and the screen had the disadvantage that the screen would shake significantly at the darkest point on the video screen.

第3図も従来の変換方式の例で、第1図に示した実施例
と異なシ、几、G、B各’l1it号に対し其々にA/
D変換器5を備えている。それゆえ、−フレームの期間
に几、G、B信号を同・象に画素1d号に変換できる。
Figure 3 is also an example of a conventional conversion method, in which A/
It is equipped with a D converter 5. Therefore, during the -frame period, the G, G, and B signals can be converted to the pixel number 1d in the same way.

しかし、この方)宍ではA/D変換器を多数個使用する
ため高価となってしまう。
However, this method uses a large number of A/D converters and is therefore expensive.

〔発明の目的〕[Purpose of the invention]

本発明の目的はセレクトスイッチのタイミングを効果的
に行なうことによシ、一画面の画像を高速にA/D変換
できる安ll1liな方法を提供するにおる。
An object of the present invention is to provide an inexpensive method of A/D converting a single screen image at high speed by effectively adjusting the timing of the select switch.

〔発明の概要〕[Summary of the invention]

本発明は一しクトスイッチの几、G、B信号への切換タ
イミングをA/D変換器のサンプリングクロンクと同期
さぜることによ)、−フレームの期間で几、G、B信号
を画素信号へ変換するようにしたものである。
In the present invention, by synchronizing the switching timing of the first switch to the 几, G, and B signals with the sampling clock of the A/D converter, the 几, G, and B signals are converted into pixels in a frame period. It is designed to convert into a signal.

〔発明の実施例〕[Embodiments of the invention]

第4図に本発明の一実施例をブロック図で示す。 FIG. 4 shows a block diagram of an embodiment of the present invention.

第5図は各部の信号波形で、これを参照しながら本発明
の詳細な説明する。
FIG. 5 shows signal waveforms at various parts, and the present invention will be explained in detail with reference to this.

第4図において、入力端子10に入力された複合画像信
号(1)はデコーダ1によって色成分を持った孔底分信
号(2)、G成分信号0)、B成分信号(4)に分けら
れて、それぞれセレクトスイッチ3へ入力され、同期分
離回路2によって分離されたライン同期信号11が、例
えば、マイコン等によって構成され、信号入出力時のタ
イミングをコントロールする制御回路4へ入力される。
In FIG. 4, a composite image signal (1) input to the input terminal 10 is divided by the decoder 1 into a hole bottom signal (2) having color components, a G component signal (0), and a B component signal (4). Line synchronization signals 11, which are input to the select switches 3 and separated by the synchronization separation circuit 2, are input to a control circuit 4, which is constituted by, for example, a microcomputer and controls the timing of inputting and outputting signals.

制御回路4は同期信号に同期し次サンプリングクロック
信号(5)を発生し、これによってA/D変換器5、メ
モリ6を制御しセレクトスイッチ3の切換タイミングを
も制御する。いま、クロックによってセレクトスイッチ
3が孔底分信号を選択したとき、A/D変換器5は孔底
分のアナログ画像信号をそのクロックタイミングでサン
プルし、デジタル画素信号に変換してメモリに記憶する
。次のす/ブリングクロックによって、セレクトスイッ
チ3はG信号を選択し、A/D変換器はこれ全受けてG
成分をデジタル化し、メモリ6に送る。メモリはクロッ
クによって別のアドレスを選択し、ここへ、デジタルG
成分を記憶する。さらに、次のクロックでセレクトスイ
ッチは孔底分に切換えられる。
The control circuit 4 generates the next sampling clock signal (5) in synchronization with the synchronization signal, thereby controlling the A/D converter 5 and the memory 6 and also controlling the switching timing of the select switch 3. Now, when the select switch 3 selects the hole bottom signal based on the clock, the A/D converter 5 samples the hole bottom analog image signal at that clock timing, converts it into a digital pixel signal, and stores it in the memory. . The select switch 3 selects the G signal by the next S/Bring clock, and the A/D converter receives all of the G signals.
The components are digitized and sent to memory 6. The memory selects another address by the clock, and here, the digital G
Remember the ingredients. Furthermore, at the next clock, the select switch is switched to the bottom of the hole.

以下同様に、上記の動作を繰p返し、−ライン中の画像
信号の几、G、B成分はデジタル画素信号に変換さ詐る
。従って、−フレームの期間で一画面分の1(、、G、
B成分は、すべてデジタル化括れ、メモリ6に収納され
る。その後、プリンタ7からの呼出1に号によって制御
回1!4はメモリ6内の画ぶ信号をプリンタ7の速度に
同期させて出力する。
Thereafter, the above operation is repeated in the same way, and the 3, G, and B components of the image signal in the - line are converted into digital pixel signals. Therefore, one screen worth of (,,G,
All B components are digitized and stored in the memory 6. Thereafter, in response to a call 1 from the printer 7, the control circuit 1!4 outputs the drawing signal in the memory 6 in synchronization with the speed of the printer 7.

このように、本システムでもカン−画像信号をデジタル
信号へと変換でき、グリツタによってカラーハードコピ
ーが得られる。
In this way, the present system can also convert a can image signal into a digital signal, and a color hard copy can be obtained using the gritter.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、安価で高速なA/D変洟方式が得られ
る。
According to the present invention, an inexpensive and high-speed A/D conversion method can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例を示すブロック図、第2図は第1図の動
作波形図、第3図は他の従来例を示すブロック図、第4
図は本発明の一実施例を示すブロック図、第5図は第4
図の各部の信号波形を示す図である。 1・・・デコーダ、3・・・セレクトスイッチ、5・・
・A/D変換器。 代理人 弁理士 高橋明夫 特開+1a60−i12388(3) 第1国 第2図 V)β〜の (3)Cr−一」11■ロ■fl二二二〕■D」lニー
=田IL−−ユLn1て二丁−一一一二I。−一(4)
 B □を二]l−二−二IL11−−−−−J■LL
L10.urニー]二τ−−二lLb、−−一−−」J
llL、、、、ど」l]ニニ〕1.、−−−−≠3国
Fig. 1 is a block diagram showing a conventional example, Fig. 2 is an operation waveform diagram of Fig. 1, Fig. 3 is a block diagram showing another conventional example, and Fig. 4 is a block diagram showing a conventional example.
The figure is a block diagram showing one embodiment of the present invention, and FIG.
It is a figure which shows the signal waveform of each part of a figure. 1...Decoder, 3...Select switch, 5...
・A/D converter. Agent Patent Attorney Akio Takahashi Unexamined Japanese Patent Publication +1a60-i12388 (3) 1st Country Figure 2 V) β ~ (3) Cr-1''11■Ro■fl222]■D''lnee=田IL- -YuLn1te2cho-1112I. -1 (4)
B □ 2] l-2-2IL11---J■LL
L10. ur knee] 2τ--2lLb,--1--"J
llL,,,,d''l]Nini]1. , -----≠3 countries

Claims (1)

【特許請求の範囲】[Claims] 1、 カラービデオ信号を色1d号に分昌′屹すゐデコ
ーダと、前記色信号を順次切換えるスイッチと、デジタ
ル信号に変換するA/D変換器とを備え、l’cアナロ
グーデジタル変換装置にJ・いて、目れ己スイッチの前
日己巳・1d号のり瑛のタイミングをA/D変換の?7
ノリング信号と同期させ心ことを特・1とするA/D変
換方沃。
1. A l'c analog-to-digital converter, comprising a decoder that divides color video signals into color number 1d, a switch that sequentially switches the color signals, and an A/D converter that converts the color signals into digital signals. J was there, and the day before the Mereki switch, was the timing of the A/D conversion of Kimi and No. 1D Noriaki? 7
This is an A/D conversion method whose special feature is synchronization with the knocking signal.
JP58219448A 1983-11-24 1983-11-24 A/d conversion method Pending JPS60112388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58219448A JPS60112388A (en) 1983-11-24 1983-11-24 A/d conversion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58219448A JPS60112388A (en) 1983-11-24 1983-11-24 A/d conversion method

Publications (1)

Publication Number Publication Date
JPS60112388A true JPS60112388A (en) 1985-06-18

Family

ID=16735568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58219448A Pending JPS60112388A (en) 1983-11-24 1983-11-24 A/d conversion method

Country Status (1)

Country Link
JP (1) JPS60112388A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625934U (en) * 1985-06-28 1987-01-14
JPS62207090A (en) * 1986-03-07 1987-09-11 Hitachi Ltd Video printer device
JPS62245865A (en) * 1986-04-18 1987-10-27 Shinko Electric Co Ltd Digitizing multivalued signal input device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS625934U (en) * 1985-06-28 1987-01-14
JPS62207090A (en) * 1986-03-07 1987-09-11 Hitachi Ltd Video printer device
JPS62245865A (en) * 1986-04-18 1987-10-27 Shinko Electric Co Ltd Digitizing multivalued signal input device

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