JPS63191702U - - Google Patents
Info
- Publication number
- JPS63191702U JPS63191702U JP8190587U JP8190587U JPS63191702U JP S63191702 U JPS63191702 U JP S63191702U JP 8190587 U JP8190587 U JP 8190587U JP 8190587 U JP8190587 U JP 8190587U JP S63191702 U JPS63191702 U JP S63191702U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- signal transmission
- chip
- tenator
- ground pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008054 signal transmission Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Non-Reversible Transmitting Devices (AREA)
- Attenuators (AREA)
Description
第１図は本考案の一実施例を示す構成説明図、
第２図はチツプアツテネータの一例を示す構成説
明図である。
１……絶縁基板、２，３，９，１０……信号伝
送パターン、４，５……アースパターン、６……
抵抗パターン、７……プリント配線板、８……切
抜き部、１１〜１４……ランドパターン。
FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention;
FIG. 2 is a configuration explanatory diagram showing an example of a chip attenuator. 1... Insulating board, 2, 3, 9, 10... Signal transmission pattern, 4, 5... Earth pattern, 6...
Resistance pattern, 7...Printed wiring board, 8...Cutout portion, 11-14...Land pattern.
Claims (1)
ターンが形成されるとともに、これら信号伝送パ
ターンおよびアースパターンを接続するように抵
抗パターンが形成された分布定数形のチツプアツ
テネータと、 チツプアツテネータの抵抗パターンに対応する
切抜き部が形成され、一方の面にはこの切抜き部
を囲むようにアースパターンが形成され、他方の
面にはチツプアツテネータの信号伝送パターンお
よびアースパターンを接続するための信号伝送パ
ターンおよび一方の面に形成されたアースパター
ンと電気的に接続された複数のランドパターンが
前記切抜き部を挟むようにして形成されたプリン
ト配線板、 とで構成されたことを特徴とするチツプアツテ
ネータの実装構造。[Claims for Utility Model Registration] A distributed constant chip attenuator in which a signal transmission pattern and a ground pattern are formed on an insulating substrate, and a resistance pattern is formed to connect the signal transmission pattern and the ground pattern. A cutout corresponding to the resistance pattern of the chip-up tenator is formed, a ground pattern is formed on one side to surround this cut-out, and a signal transmission pattern and a ground pattern of the chip-up tenator are formed on the other side. A printed wiring board including a signal transmission pattern for connection, a ground pattern formed on one surface, and a plurality of electrically connected land patterns sandwiching the cutout. The mounting structure of the chip-up tenator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8190587U JPH0419845Y2 (en) | 1987-05-28 | 1987-05-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8190587U JPH0419845Y2 (en) | 1987-05-28 | 1987-05-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63191702U true JPS63191702U (en) | 1988-12-09 |
| JPH0419845Y2 JPH0419845Y2 (en) | 1992-05-07 |
Family
ID=30934069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8190587U Expired JPH0419845Y2 (en) | 1987-05-28 | 1987-05-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419845Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007060084A (en) * | 2005-08-23 | 2007-03-08 | Yokogawa Electric Corp | Arttenuator |
-
1987
- 1987-05-28 JP JP8190587U patent/JPH0419845Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007060084A (en) * | 2005-08-23 | 2007-03-08 | Yokogawa Electric Corp | Arttenuator |
| JP4508037B2 (en) * | 2005-08-23 | 2010-07-21 | 横河電機株式会社 | Attenuator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0419845Y2 (en) | 1992-05-07 |
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