JPH0470759U - - Google Patents

Info

Publication number
JPH0470759U
JPH0470759U JP11331390U JP11331390U JPH0470759U JP H0470759 U JPH0470759 U JP H0470759U JP 11331390 U JP11331390 U JP 11331390U JP 11331390 U JP11331390 U JP 11331390U JP H0470759 U JPH0470759 U JP H0470759U
Authority
JP
Japan
Prior art keywords
wiring patterns
electrically connected
short
insulating substrate
patterns electrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11331390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11331390U priority Critical patent/JPH0470759U/ja
Publication of JPH0470759U publication Critical patent/JPH0470759U/ja
Pending legal-status Critical Current

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  • Structure Of Printed Boards (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のプリント基板の一実施例を示
す平面図、第2図は従来のプリント基板の一例を
示す平面図である。 1,11……絶縁基板、2,2′,12……ラ
ンド、3,4,13,14……スルーホール、5
,5′……太い配線パターン、6,6′……細い
配線パターン。
FIG. 1 is a plan view showing an embodiment of the printed circuit board of the present invention, and FIG. 2 is a plan view showing an example of a conventional printed circuit board. 1, 11... Insulating substrate, 2, 2', 12... Land, 3, 4, 13, 14... Through hole, 5
, 5'... Thick wiring pattern, 6, 6'... Thin wiring pattern.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 格子状に貫通穴をあけて配列した複数のスルー
ホールを有する絶縁基板と、前記各スルーホール
のまわりに設けた複数のランドと、前記絶縁基板
の一方面上で前記格子状の縦方向の各列ごとに前
記各ランドと第1の短く細い配線パターンを介し
て電気的に接続した複数の第1の太い配線パター
ンと、前記絶縁基板の他方面上で前記格子状の横
方向の各行ごとに前記各ランドと第2の短く細い
配線パターンを介して電気的に接続した複数の第
2の太い配線パターンとを備えることを特徴とす
るプリント基板。
an insulating substrate having a plurality of through holes arranged in a grid pattern; a plurality of lands provided around each of the through holes; a plurality of first thick wiring patterns electrically connected to each land via a first short thin wiring pattern for each column; and a plurality of first thick wiring patterns electrically connected to each land via a first short thin wiring pattern, and for each row in the horizontal direction of the grid on the other surface of the insulating substrate. A printed circuit board comprising a plurality of second thick wiring patterns electrically connected to each of the lands via second short and thin wiring patterns.
JP11331390U 1990-10-29 1990-10-29 Pending JPH0470759U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11331390U JPH0470759U (en) 1990-10-29 1990-10-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11331390U JPH0470759U (en) 1990-10-29 1990-10-29

Publications (1)

Publication Number Publication Date
JPH0470759U true JPH0470759U (en) 1992-06-23

Family

ID=31860881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11331390U Pending JPH0470759U (en) 1990-10-29 1990-10-29

Country Status (1)

Country Link
JP (1) JPH0470759U (en)

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