JPH0379476U - - Google Patents

Info

Publication number
JPH0379476U
JPH0379476U JP14085089U JP14085089U JPH0379476U JP H0379476 U JPH0379476 U JP H0379476U JP 14085089 U JP14085089 U JP 14085089U JP 14085089 U JP14085089 U JP 14085089U JP H0379476 U JPH0379476 U JP H0379476U
Authority
JP
Japan
Prior art keywords
electrical elements
circuit board
printed circuit
wiring pattern
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14085089U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14085089U priority Critical patent/JPH0379476U/ja
Publication of JPH0379476U publication Critical patent/JPH0379476U/ja
Pending legal-status Critical Current

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Landscapes

  • Manufacturing Of Printed Wiring (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の実施例を示すもので、第1図は
回路全体を示す平面図、第2図は本考案の要部断
面図である。 10……プリント基板、11……プリント配線
、13……パワートラジスタ、15……バスバー
、16……電力供給ライン、17……半田、17
a……半田層。
The drawings show an embodiment of the present invention, and FIG. 1 is a plan view showing the entire circuit, and FIG. 2 is a sectional view of the main part of the present invention. 10... Printed circuit board, 11... Printed wiring, 13... Power transistor, 15... Bus bar, 16... Power supply line, 17... Solder, 17
a...Solder layer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基板上に抵抗等の電気素子を配置し、この電気
素子同士をエツチング等によつて形成した配線パ
ターンで接続したプリント基板において、前記配
線パターン上に電気素子同士を接続する半田層を
形成したことを特徴とするプリント基板の配線構
造。
In a printed circuit board in which electrical elements such as resistors are arranged on a substrate and these electrical elements are connected to each other by a wiring pattern formed by etching etc., a solder layer is formed on the wiring pattern to connect the electrical elements to each other. A printed circuit board wiring structure characterized by:
JP14085089U 1989-12-05 1989-12-05 Pending JPH0379476U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14085089U JPH0379476U (en) 1989-12-05 1989-12-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14085089U JPH0379476U (en) 1989-12-05 1989-12-05

Publications (1)

Publication Number Publication Date
JPH0379476U true JPH0379476U (en) 1991-08-13

Family

ID=31687792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14085089U Pending JPH0379476U (en) 1989-12-05 1989-12-05

Country Status (1)

Country Link
JP (1) JPH0379476U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245859B2 (en) * 1978-02-16 1987-09-29 Nippon Kayaku Kk

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6245859B2 (en) * 1978-02-16 1987-09-29 Nippon Kayaku Kk

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