JPS63167734U - - Google Patents
Info
- Publication number
- JPS63167734U JPS63167734U JP1987061720U JP6172087U JPS63167734U JP S63167734 U JPS63167734 U JP S63167734U JP 1987061720 U JP1987061720 U JP 1987061720U JP 6172087 U JP6172087 U JP 6172087U JP S63167734 U JPS63167734 U JP S63167734U
- Authority
- JP
- Japan
- Prior art keywords
- pad electrode
- electrode
- bump
- center
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Description
第１図ａは本考案の一実施例の断面図、第１図
ｂは本考案の一実施例の平面図、第２図は本考案
の他の実施例の平面図である。 １……半導体素子、２……パツシベーシヨン、
３……アルミニウムパツド電極、４……バリア金
属層Ａ、５……バリア金属層Ｂ、６……はんだバ
ンプ電極、７……バリア金属層境界、８……コン
タクト孔。
ｂは本考案の一実施例の平面図、第２図は本考案
の他の実施例の平面図である。 １……半導体素子、２……パツシベーシヨン、
３……アルミニウムパツド電極、４……バリア金
属層Ａ、５……バリア金属層Ｂ、６……はんだバ
ンプ電極、７……バリア金属層境界、８……コン
タクト孔。
Claims (1)
- 半導体チツプ内に形成された素子に接続された
パツド電極上にバンプ電極を形成して成るフリツ
プチツプ型半導体装置において、前記パツド電極
の中心と、前記バンプ電極の前記パツド電極との
接合面中心とが一致しないように前記バンプ電極
を配置したことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987061720U JPS63167734U (ja) | 1987-04-22 | 1987-04-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987061720U JPS63167734U (ja) | 1987-04-22 | 1987-04-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63167734U true JPS63167734U (ja) | 1988-11-01 |
Family
ID=30895322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987061720U Pending JPS63167734U (ja) | 1987-04-22 | 1987-04-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63167734U (ja) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154643A (ja) * | 1984-01-25 | 1985-08-14 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
-
1987
- 1987-04-22 JP JP1987061720U patent/JPS63167734U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154643A (ja) * | 1984-01-25 | 1985-08-14 | Hitachi Micro Comput Eng Ltd | 半導体装置 |