JPS6413144U - - Google Patents
Info
- Publication number
- JPS6413144U JPS6413144U JP10542987U JP10542987U JPS6413144U JP S6413144 U JPS6413144 U JP S6413144U JP 10542987 U JP10542987 U JP 10542987U JP 10542987 U JP10542987 U JP 10542987U JP S6413144 U JPS6413144 U JP S6413144U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- heat sink
- chip
- hole
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Description
第1図は本考案の一実施例を断面で示すもので
第2図の−線に沿う断面図、第2図は第1図
のものの平面図、第3図a,bは接合前の状態を
示す平面図、第4図a,bは第3図のそれぞれa
,b線に沿つた断面図である。 1……放熱板、2……接着剤、3……切欠き、
4……基板、5……ICチツプ、6……ワイヤ、
7……端子。
第2図の−線に沿う断面図、第2図は第1図
のものの平面図、第3図a,bは接合前の状態を
示す平面図、第4図a,bは第3図のそれぞれa
,b線に沿つた断面図である。 1……放熱板、2……接着剤、3……切欠き、
4……基板、5……ICチツプ、6……ワイヤ、
7……端子。
Claims (1)
- 良熱伝導材からなる放熱板の上面に一部に孔ま
たは切欠きを設けた積層状態の基板を接合し、該
基板の前記孔または切欠きにICチツプをその下
面が前記放熱板に接するようにして挿入し、該I
Cチツプのボンデイングパツドと前記積層状態の
各基板との間をボンデイングワイヤにより接続し
た集積回路素子を2枚製作し、該2枚の集積回路
素子を前記放熱板の部分において背中合せに接着
したことを特徴とする集積回路素子の保持構造。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10542987U JPH0610718Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10542987U JPH0610718Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6413144U true JPS6413144U (ja) | 1989-01-24 |
JPH0610718Y2 JPH0610718Y2 (ja) | 1994-03-16 |
Family
ID=31338034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10542987U Expired - Lifetime JPH0610718Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0610718Y2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019009466A (ja) * | 2014-11-20 | 2019-01-17 | 日本精工株式会社 | 電子部品搭載用放熱基板 |
-
1987
- 1987-07-09 JP JP10542987U patent/JPH0610718Y2/ja not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019009466A (ja) * | 2014-11-20 | 2019-01-17 | 日本精工株式会社 | 電子部品搭載用放熱基板 |
JP2019009465A (ja) * | 2014-11-20 | 2019-01-17 | 日本精工株式会社 | 電子部品搭載用放熱基板 |
JP2019041110A (ja) * | 2014-11-20 | 2019-03-14 | 日本精工株式会社 | 電子部品搭載用放熱基板 |
Also Published As
Publication number | Publication date |
---|---|
JPH0610718Y2 (ja) | 1994-03-16 |