JPS6219751U - - Google Patents
Info
- Publication number
- JPS6219751U JPS6219751U JP1985111171U JP11117185U JPS6219751U JP S6219751 U JPS6219751 U JP S6219751U JP 1985111171 U JP1985111171 U JP 1985111171U JP 11117185 U JP11117185 U JP 11117185U JP S6219751 U JPS6219751 U JP S6219751U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chip
- printed wiring
- wiring board
- bonded
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Description
第１図は本考案のＩＣパツケージを説明するた
めの縦断面図、第２図は従来のＩＣパツケージを
説明するための縦断面図である。 １……ＩＣパツケージ、２……プリント配線基
板、３……セラミツク基板、４……接着材、５…
…スルーホール、６……ボンデイング用電極、７
……ＩＣチツプ、８……ボンデイング用パツド、
９……ボンデイングワイヤ、１０……ピン。
めの縦断面図、第２図は従来のＩＣパツケージを
説明するための縦断面図である。 １……ＩＣパツケージ、２……プリント配線基
板、３……セラミツク基板、４……接着材、５…
…スルーホール、６……ボンデイング用電極、７
……ＩＣチツプ、８……ボンデイング用パツド、
９……ボンデイングワイヤ、１０……ピン。
Claims (1)
- ＩＣ用パツケージにおいて、ＩＣチツプを搭載
する部分を熱伝導性の良好な材料からなる基板と
し、該基板をプリント配線基板に接着した構造を
特徴とするＩＣパツケージ。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985111171U JPS6219751U (ja) | 1985-07-19 | 1985-07-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985111171U JPS6219751U (ja) | 1985-07-19 | 1985-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6219751U true JPS6219751U (ja) | 1987-02-05 |
Family
ID=30990845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985111171U Pending JPS6219751U (ja) | 1985-07-19 | 1985-07-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6219751U (ja) |
-
1985
- 1985-07-19 JP JP1985111171U patent/JPS6219751U/ja active Pending