JPS6457641U - - Google Patents

Info

Publication number
JPS6457641U
JPS6457641U JP15065787U JP15065787U JPS6457641U JP S6457641 U JPS6457641 U JP S6457641U JP 15065787 U JP15065787 U JP 15065787U JP 15065787 U JP15065787 U JP 15065787U JP S6457641 U JPS6457641 U JP S6457641U
Authority
JP
Japan
Prior art keywords
electrode
chip
insulating film
lead frame
island
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15065787U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15065787U priority Critical patent/JPS6457641U/ja
Publication of JPS6457641U publication Critical patent/JPS6457641U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は一実施例を示す平面図、第２図は第１
図のＡ―Ａ線位置での断面図、第３図は他の実施
例を示す断面図、第４図は従来の実装体を示す平
面図、第５図は第４図のＢ―Ｂ線位置での断面図
である。 １……アイランド、２……インナーリード、３
……ＩＣチツプ、４……パツド、１１……第１の
電極、１２……第２の電極、１３……配線、１４
，１５……ワイヤ、１６……バンプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードフレームのアイランド上に絶縁フイルム
    が貼りつけられ、その絶縁フイルム上にはＩＣチ
    ツプのパツドと接続された第１の電極、リードフ
    レームのインナーリードと接続された第２の電極
    、及び両電極間を接続する配線とが設けられてお
    り、ＩＣチツプが前記第１の電極と接続されて取
    りつけられ封止されているワイヤボンデイング実
    装体。
JP15065787U 1987-09-30 1987-09-30 Pending JPS6457641U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15065787U JPS6457641U (ja) 1987-09-30 1987-09-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15065787U JPS6457641U (ja) 1987-09-30 1987-09-30

Publications (1)

Publication Number Publication Date
JPS6457641U true JPS6457641U (ja) 1989-04-10

Family

ID=31423997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15065787U Pending JPS6457641U (ja) 1987-09-30 1987-09-30

Country Status (1)

Country Link
JP (1) JPS6457641U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0372585A (ja) * 1989-05-29 1991-03-27 Tomoegawa Paper Co Ltd 接着シート及び半導体装置
JPH03169693A (ja) * 1989-11-30 1991-07-23 Toshiba Corp カード状電子機器およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192334A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 半導体装置
JPS622628A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置
JPS62265733A (ja) * 1986-05-13 1987-11-18 Nec Corp 混成集積回路装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58192334A (ja) * 1982-05-07 1983-11-09 Hitachi Ltd 半導体装置
JPS622628A (ja) * 1985-06-28 1987-01-08 Toshiba Corp 半導体装置
JPS62265733A (ja) * 1986-05-13 1987-11-18 Nec Corp 混成集積回路装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0372585A (ja) * 1989-05-29 1991-03-27 Tomoegawa Paper Co Ltd 接着シート及び半導体装置
JPH03169693A (ja) * 1989-11-30 1991-07-23 Toshiba Corp カード状電子機器およびその製造方法

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