JPH0474461U - - Google Patents
Info
- Publication number
- JPH0474461U JPH0474461U JP11833090U JP11833090U JPH0474461U JP H0474461 U JPH0474461 U JP H0474461U JP 11833090 U JP11833090 U JP 11833090U JP 11833090 U JP11833090 U JP 11833090U JP H0474461 U JPH0474461 U JP H0474461U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- metal film
- film leads
- pasted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims 2
- 239000004642 Polyimide Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図はこの考案の一実施例である半導体装置
用パツケージの部分断面斜視図、第2図は従来の
半導体装置用パツケージの部分断面斜視図である
。 図において、1は半導体装置、2は金線、3は
リード部、5は封止樹脂、6はポリミイドシート
を示す。なお、図中、同一符号は同一、または相
当部分を示す。
用パツケージの部分断面斜視図、第2図は従来の
半導体装置用パツケージの部分断面斜視図である
。 図において、1は半導体装置、2は金線、3は
リード部、5は封止樹脂、6はポリミイドシート
を示す。なお、図中、同一符号は同一、または相
当部分を示す。
Claims (1)
- 半導体装置表面に金属膜リードを備えた絶縁シ
ートを貼り付け、前記金属膜リードが前記半導体
装置の電極とワイヤボンドにより、電気的に接続
されるインナーリード部と、樹脂封止後パツケー
ジ外部に露出するアウターリードを兼ねた事を特
徴とする半導体装置用パツケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11833090U JPH0474461U (ja) | 1990-11-08 | 1990-11-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11833090U JPH0474461U (ja) | 1990-11-08 | 1990-11-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0474461U true JPH0474461U (ja) | 1992-06-30 |
Family
ID=31866248
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11833090U Pending JPH0474461U (ja) | 1990-11-08 | 1990-11-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0474461U (ja) |
-
1990
- 1990-11-08 JP JP11833090U patent/JPH0474461U/ja active Pending