JPS622248U - - Google Patents
Info
- Publication number
- JPS622248U JPS622248U JP1985092498U JP9249885U JPS622248U JP S622248 U JPS622248 U JP S622248U JP 1985092498 U JP1985092498 U JP 1985092498U JP 9249885 U JP9249885 U JP 9249885U JP S622248 U JPS622248 U JP S622248U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit chip
- bonding
- fixed
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 2
- 229910000679 solder Inorganic materials 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Wire Bonding (AREA)
Description
第1図は本考案の第一の実施例を示す斜視図、
第2図は第1図のA―A断面図、第3図は本考案
の他の実施例を示す斜視図である。 1,2……集積回路チツプ、3……集積回路パ
ツケージ、4a,4b,5a,5b……ボンデイ
ングパツド、6a,6b……ボンデイングワイヤ
、7,8,9,10……小形集積回路チツプ、1
1,12,13,21,22……半田バンプ、1
3……半導体ウエハ、14……大形集積回路チツ
プ、15,16,25,26……導体ランド。
第2図は第1図のA―A断面図、第3図は本考案
の他の実施例を示す斜視図である。 1,2……集積回路チツプ、3……集積回路パ
ツケージ、4a,4b,5a,5b……ボンデイ
ングパツド、6a,6b……ボンデイングワイヤ
、7,8,9,10……小形集積回路チツプ、1
1,12,13,21,22……半田バンプ、1
3……半導体ウエハ、14……大形集積回路チツ
プ、15,16,25,26……導体ランド。
Claims (1)
- 半田付け可能な複数個の第一の導体ランドを有
し、第一の論理回路を構成する第一の集積回路チ
ツプと、前記第一の導体ランドをおのおの半田接
続される複数個の第二の導体ランドおよび複数個
の第一のボンデングパツドを表面に配設され、前
記第一の集積回路チツプを前記半田接続により表
面上に固定し、第二の論理回路を構成する第二の
集積回路チツプと、前記第二の集積回路チツプを
表面に固定され、複数個のボンデイングワイヤで
前記第一のボンデングパツドを接続される第二の
ボンデイングパツドを有する集積回路パツケージ
とを具備することを特徴とする集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985092498U JPS622248U (ja) | 1985-06-19 | 1985-06-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1985092498U JPS622248U (ja) | 1985-06-19 | 1985-06-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS622248U true JPS622248U (ja) | 1987-01-08 |
Family
ID=30649351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1985092498U Pending JPS622248U (ja) | 1985-06-19 | 1985-06-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS622248U (ja) |
-
1985
- 1985-06-19 JP JP1985092498U patent/JPS622248U/ja active Pending