JPS63150321U - - Google Patents

Description

[Brief explanation of drawings]

Figures 1 to 3 show one embodiment of the present invention, with Figure 1 being a block diagram showing the circuit configuration, and Figure 2 being a block diagram showing the circuit configuration.
3 are timing charts showing signal states at each part of FIG. 1, and FIG. 4 is a timing chart showing output signal waveforms of phase A and phase B during forward and reverse rotation of the incremental encoder. 1... Clock pulse generation circuit, 2, 7... Delay circuit, 3, 4... Register, 5... Comparison circuit,
6...monostable multi-circuit, 8...logic circuit.

Claims (1)

[Claims for Utility Model Registration] A terminal into which either a pure binary code or a binary coded decimal code signal is input, a clock pulse generation circuit, and a first clock pulse that delays the clock pulse output from the clock pulse generation circuit. a delay circuit; a first register that latches the input signal from the terminal using a clock pulse delayed by the first delay circuit; and a second register that latches the contents of the first register using a clock pulse generated by the clock pulse. a comparator circuit that compares the contents of the second register with the input signal from the terminal, and generates a pulse signal with a cycle less than one cycle of the clock pulse according to the comparison result of the comparator circuit. A monostable multi-circuit, a second delay circuit that delays and outputs the pulse signal generated by the monostable multi-circuit, and A-phase and B-phase outputs from the outputs of the monostable multi-circuit and the second delay circuit. An encoder signal generation circuit comprising: a logic circuit that generates an encoder signal.