JPS63128636A - 半導体集積回路装置 - Google Patents

半導体集積回路装置

Info

Publication number
JPS63128636A
JPS63128636A JP61275908A JP27590886A JPS63128636A JP S63128636 A JPS63128636 A JP S63128636A JP 61275908 A JP61275908 A JP 61275908A JP 27590886 A JP27590886 A JP 27590886A JP S63128636 A JPS63128636 A JP S63128636A
Authority
JP
Japan
Prior art keywords
pad
wafer
probe
metal
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61275908A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0517706B2 (enExample
Inventor
Hideo Ishikawa
石川　英郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61275908A priority Critical patent/JPS63128636A/ja
Publication of JPS63128636A publication Critical patent/JPS63128636A/ja
Publication of JPH0517706B2 publication Critical patent/JPH0517706B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
JP61275908A 1986-11-18 1986-11-18 半導体集積回路装置 Granted JPS63128636A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61275908A JPS63128636A (ja) 1986-11-18 1986-11-18 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61275908A JPS63128636A (ja) 1986-11-18 1986-11-18 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS63128636A true JPS63128636A (ja) 1988-06-01
JPH0517706B2 JPH0517706B2 (enExample) 1993-03-09

Family

ID=17562106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61275908A Granted JPS63128636A (ja) 1986-11-18 1986-11-18 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS63128636A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475236A (en) * 1991-09-02 1995-12-12 Fujitsu Limited Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process
US5616931A (en) * 1994-08-24 1997-04-01 Nec Corporation Semiconductor device
JP2006147601A (ja) * 2004-11-16 2006-06-08 Matsushita Electric Ind Co Ltd 半導体ウェハーおよびその検査方法
JP2010190737A (ja) * 2009-02-18 2010-09-02 Seiko Instruments Inc 半導体検査装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5475236A (en) * 1991-09-02 1995-12-12 Fujitsu Limited Semiconductor chip for mounting on a semiconductor package substrate by a flip-clip process
US5616931A (en) * 1994-08-24 1997-04-01 Nec Corporation Semiconductor device
GB2292637B (en) * 1994-08-24 1998-07-22 Nec Corp Semiconductor device
JP2006147601A (ja) * 2004-11-16 2006-06-08 Matsushita Electric Ind Co Ltd 半導体ウェハーおよびその検査方法
JP2010190737A (ja) * 2009-02-18 2010-09-02 Seiko Instruments Inc 半導体検査装置

Also Published As

Publication number Publication date
JPH0517706B2 (enExample) 1993-03-09

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