JPS63127541A - チップの接合方法 - Google Patents

チップの接合方法

Info

Publication number
JPS63127541A
JPS63127541A JP61273280A JP27328086A JPS63127541A JP S63127541 A JPS63127541 A JP S63127541A JP 61273280 A JP61273280 A JP 61273280A JP 27328086 A JP27328086 A JP 27328086A JP S63127541 A JPS63127541 A JP S63127541A
Authority
JP
Japan
Prior art keywords
chip
substrate
adhesive
bump
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61273280A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0482184B2 (enExample
Inventor
Noriyuki Inagaki
典之 稲垣
Yutaka Makino
豊 牧野
Akihiro Yamamoto
章博 山本
Shinya Matsumura
信弥 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61273280A priority Critical patent/JPS63127541A/ja
Publication of JPS63127541A publication Critical patent/JPS63127541A/ja
Publication of JPH0482184B2 publication Critical patent/JPH0482184B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)
JP61273280A 1986-11-17 1986-11-17 チップの接合方法 Granted JPS63127541A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61273280A JPS63127541A (ja) 1986-11-17 1986-11-17 チップの接合方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61273280A JPS63127541A (ja) 1986-11-17 1986-11-17 チップの接合方法

Publications (2)

Publication Number Publication Date
JPS63127541A true JPS63127541A (ja) 1988-05-31
JPH0482184B2 JPH0482184B2 (enExample) 1992-12-25

Family

ID=17525645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61273280A Granted JPS63127541A (ja) 1986-11-17 1986-11-17 チップの接合方法

Country Status (1)

Country Link
JP (1) JPS63127541A (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02234447A (ja) * 1989-03-07 1990-09-17 Nec Corp 半導体集積回路素子の接続方法
US5037780A (en) * 1989-02-02 1991-08-06 Matsushita Electric Industrial Co., Ltd. Method for attaching semiconductors to a transparent substrate using a light-curable resin
US5766972A (en) * 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
JP2005028202A (ja) * 2003-07-07 2005-02-03 Hitachi Industries Co Ltd テーブル平行度調整装置とそれを用いたディスペンサ
JP2009030270A (ja) * 2007-07-25 2009-02-12 Panasonic Electric Works Co Ltd 床材
JP2010034585A (ja) * 2009-11-06 2010-02-12 Toray Eng Co Ltd チップ実装装置における平行度調整方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262430A (ja) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60262430A (ja) * 1984-06-08 1985-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5037780A (en) * 1989-02-02 1991-08-06 Matsushita Electric Industrial Co., Ltd. Method for attaching semiconductors to a transparent substrate using a light-curable resin
JPH02234447A (ja) * 1989-03-07 1990-09-17 Nec Corp 半導体集積回路素子の接続方法
US5766972A (en) * 1994-06-02 1998-06-16 Mitsubishi Denki Kabushiki Kaisha Method of making resin encapsulated semiconductor device with bump electrodes
JP2005028202A (ja) * 2003-07-07 2005-02-03 Hitachi Industries Co Ltd テーブル平行度調整装置とそれを用いたディスペンサ
JP2009030270A (ja) * 2007-07-25 2009-02-12 Panasonic Electric Works Co Ltd 床材
JP2010034585A (ja) * 2009-11-06 2010-02-12 Toray Eng Co Ltd チップ実装装置における平行度調整方法

Also Published As

Publication number Publication date
JPH0482184B2 (enExample) 1992-12-25

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