JPS63127541A - Method of bonding chip - Google Patents
Method of bonding chipInfo
- Publication number
- JPS63127541A JPS63127541A JP61273280A JP27328086A JPS63127541A JP S63127541 A JPS63127541 A JP S63127541A JP 61273280 A JP61273280 A JP 61273280A JP 27328086 A JP27328086 A JP 27328086A JP S63127541 A JPS63127541 A JP S63127541A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- adhesive
- lead
- bump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000000853 adhesive Substances 0.000 claims abstract description 28
- 230000001070 adhesive effect Effects 0.000 claims abstract description 28
- 238000003825 pressing Methods 0.000 claims abstract description 10
- 230000001678 irradiating effect Effects 0.000 claims abstract 2
- 238000001514 detection method Methods 0.000 description 12
- 239000002313 adhesive film Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はチップの接合方法に関し、特に7リツブチツプ
のようにチップの一側面に形成されたバンプ接点を基板
のリードに電気的に接続すると同時にチップを基板に固
定するチップの接合方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for bonding chips, and in particular to a method for bonding chips, in particular a method for electrically connecting a bump contact formed on one side of a chip, such as a 7-rib chip, to a lead on a substrate and simultaneously bonding the chip. The present invention relates to a method for bonding a chip to a substrate.
従来の技術
従来から、バンプ接点を有するチップの接合方法として
、金属間接合による接合方法が種々提案されている。例
えば、本出願人は先に第7図に示すような接合方法を提
案している。即ち、チップ41をそのバンプ接7点を上
向きにした状態で粘着性フィルム42にて保持するとと
もにこの粘着性フィルム42をウェハリング43を介し
て位置決め装置44にて位置決めし、このチップ41を
図示しない吸着コレットを備えた移送りtWlにて、昇
降可能でかつチップを真空吸着するように構成された押
圧体45の載置面46上に移載し、この載置面46上の
チップ位置を上方に配置した位置検出装置47にて検出
するとともにその位置検出に応じて押圧体45を位置決
め装置48にて位置補正し、さらに基板位置決め装置5
2にて前記押圧体45の上方の水平面上で基板51を移
動させるとともに、基板位置検出装置53で基板51の
位置を検出して基板51のチップ接合位置を前記載置面
46上のチップ41の直上に位置させ、その後押圧体4
5を上昇させて基板51にチップ41を加圧するととも
に、熱又は超音波を印加して、チップ41のバンブ接点
を基板51のリードに接合する方法を提案した。2. Description of the Related Art Conventionally, various joining methods using metal-to-metal bonding have been proposed as methods for joining chips having bump contacts. For example, the present applicant has previously proposed a joining method as shown in FIG. That is, the chip 41 is held with an adhesive film 42 with its seven bump contact points facing upward, and the adhesive film 42 is positioned by a positioning device 44 via a wafer ring 43. The chip is transferred onto the mounting surface 46 of the pressing body 45, which can be raised and lowered and is configured to vacuum-adsorb the chip, using a transporter tWl equipped with a suction collet, and the chip position on the mounting surface 46 is adjusted. The position of the pressing body 45 is detected by the position detection device 47 disposed above, and the position of the pressing body 45 is corrected by the positioning device 48 according to the detected position, and further the substrate positioning device 5
2, the substrate 51 is moved on the horizontal plane above the pressing body 45, and the substrate position detection device 53 detects the position of the substrate 51 to determine the chip bonding position of the substrate 51 between the chips 41 on the mounting surface 46. , and then press the pressing body 4
proposed a method of joining the bump contacts of the chip 41 to the leads of the substrate 51 by raising the chip 41 to press the chip 41 against the substrate 51 and applying heat or ultrasonic waves.
発明が解決しようとする問題、α
ところで、上記チップの接合方法においては、接合面に
圧力を加えながら熱又は超、音波を加えて金属間接合を
行い、チップの固定と電気的接合を同時に行うようにし
ているため、基板やチップに熱や超音波を印加しなけれ
ばならないという問題があるとともに、僅かな条件の相
違によっても確実に接合できない場合が生じるという問
題があった。Problem to be solved by the invention α By the way, in the above chip joining method, metal-to-metal joining is performed by applying heat, ultrasonic waves, or sound waves while applying pressure to the joining surface, and fixing of the chip and electrical joining are simultaneously performed. As a result, there is a problem in that heat or ultrasonic waves must be applied to the substrate or chip, and there is also a problem in that reliable bonding may not be possible even due to slight differences in conditions.
本発明は上記従来の問題点に鑑み、基板に対してチップ
を押圧することにより、バンプ接点とリードを電気的に
接続した状態でチップを基板に対して確実に固定できる
チップの接合方法を提供することを目的とする。In view of the above-mentioned conventional problems, the present invention provides a chip bonding method that can reliably fix the chip to the substrate while the bump contacts and leads are electrically connected by pressing the chip against the substrate. The purpose is to
問題点を解決するための手段
本発明は上記目的を達成するため、バンプ接点を形成さ
れたチップの一側面又は基板のチップ接合面に紫外線硬
化型の接着剤を塗布する工程と、チップのバンプ接点を
基板のリードに圧検させるようにチップと基板を加圧す
る工程と、この加圧状態で前記接着剤に紫外線を照射し
て接着剤を硬化させ、バンプ接点とリードを圧接させて
電気的に接続した状態でチップを基板に固定する工程と
を備えていることを特徴とする。Means for Solving the Problems In order to achieve the above object, the present invention includes a step of applying an ultraviolet curable adhesive to one side of a chip on which a bump contact is formed or a chip bonding surface of a substrate, and There is a step of pressurizing the chip and the board so that the contacts are pressed against the leads of the board, and in this pressurized state, the adhesive is irradiated with ultraviolet rays to harden the adhesive, and the bump contacts and the leads are pressed together to form an electrical connection. and fixing the chip to the substrate in a state where the chip is connected to the substrate.
又、本発明に係る第2発明は、チップと基板を加圧する
工程に先立って、バンプ接点を形成されたチップの一側
面と基板のチップ接合面との平行調整を行う工程を備え
ていることを特徴とする。Further, a second aspect of the present invention is that, prior to the step of pressurizing the chip and the substrate, the method includes a step of adjusting parallelism between one side of the chip on which the bump contact is formed and the chip bonding surface of the substrate. It is characterized by
作用
本発明は上記構成を有するので、バンプ接点を有するチ
ップを基板に接合するのに、接着剤を用いて接合してお
り、熱や超音波を印加する必要がないので、装置が簡単
になるとともに容易かつ確実にチップを基板に固定する
ことができ、しかもバンプ接点をリードに圧接して電気
的接続を確保した状態でその*ま接着剤を硬化させて接
合しているので、接着剤の硬化による機械的接合完了後
、加圧を解除してもバンプ接点はその弾性復元力によっ
てリードに圧接されて電気的接続が保持され、機械的並
びに電気的接合を確実に得ることができる。Function: Since the present invention has the above configuration, the chip having bump contacts is bonded to the substrate using an adhesive, and there is no need to apply heat or ultrasonic waves, which simplifies the device. The chip can be easily and reliably fixed to the board, and since the bump contacts are pressure-contacted to the leads to ensure electrical connection, the adhesive is cured and bonded. After completion of mechanical bonding due to hardening, even if the pressure is removed, the bump contacts are pressed against the leads due to their elastic restoring force, and electrical connection is maintained, so that mechanical and electrical bonding can be reliably obtained.
また、チップと基板の加圧時にそれらの平行調整を行う
ことにより、接合面が確実に圧接し、信頼性の高い電気
的接合状態を得ることができる。Further, by adjusting the parallelism between the chip and the substrate when pressurizing them, the bonding surfaces can be reliably pressed against each other, and a highly reliable electrical bonding state can be obtained.
実施例
以下、本発明の一実施例を第1図〜第6図を参照しなが
ら説明する。EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 6.
第5図において、1はICチップ等のチップで、その−
側面にはバンプ接点2が突出して設けられており、この
バンプ接点2が基板3のチップ装着面に形成されたり−
ド4に電気的に接続される。In Fig. 5, 1 is a chip such as an IC chip, and its -
A bump contact 2 is provided protruding from the side surface, and this bump contact 2 is formed on the chip mounting surface of the board 3.
It is electrically connected to the card 4.
前記チップ1はチップテーブル5の上端の加圧台5a上
に図示しない移送装置にてチップ供給部から移載される
。前記チップテーブル5は、下方からX軸方向に移動す
るXテーブル6と、X軸に直角なY軸方向に移動するY
テーブル7と、X軸及びY軸に直角なZ軸を中心として
回転するθテープル8と、Z軸方向に移動するZテーブ
ル9と、X紬及びY釉に平行な軸回りに揺動可能な平行
調整テーブル10とから構成されている。一方、前記基
板3は、透明なプラス基板にて構成され、そのチップ装
着面の適当な位置に位置決め用の基準標識(図示せず)
が設けられている。この基板3は、前記チップテーブル
5の上方に配設された基板移動装置11に保持具12に
てチップ装着面を下向きにして保持されている。この基
板移動装置11はチップテーブル5の上方位置とその側
方に退避した位置との間で移動可能にかつ保持した基板
3の任意の位置を前記チップテーブル5の加圧台5aの
中心位置に正確に対向するように位置決め可能に構成さ
れ、基板移動装置11が退避位置に位置するときに、図
示しない基板供給取出装置にて基板3が供給されるとと
もにチップ1を装着された基板3を取出すように構成さ
れている。又、基板移動装置11の基板3の背面が当接
するが支持板11+zには、前記基板に設けられた基準
標識の配置位置とチップ装着位置に対応して貫通孔13
が!?!設されている。14は、前記基板移動装置11
の上方に配設された作業台で、CCTVカメラを有する
焦点検出装置付顕微鏡15と、接着剤を滴下するディス
ペンサから成る接着剤塗布装置16と、紫外線照射具1
7とが並設されており、Z軸方向に移動可能にかつ上記
各装置の配設方向に移動可能に構成されている。前記紫
外線照射具17には、シャッターを有する水銀灯i4:
18より光7アイパー19を経て紫外線が導かれている
。The chips 1 are transferred from the chip supply section onto the pressure table 5a at the upper end of the chip table 5 by a transfer device (not shown). The chip table 5 includes an X table 6 that moves from below in the X-axis direction and a Y-table that moves in the Y-axis direction perpendicular to the X-axis.
The table 7, the θ table 8 that rotates around the Z axis perpendicular to the X and Y axes, the Z table 9 that moves in the Z axis direction, and can swing around an axis parallel to the X pongee and Y glaze. It is composed of a parallel adjustment table 10. On the other hand, the substrate 3 is made of a transparent positive substrate, and a reference mark (not shown) for positioning is placed at an appropriate position on the chip mounting surface.
is provided. This substrate 3 is held by a substrate moving device 11 disposed above the chip table 5 with a holder 12 with the chip mounting surface facing downward. This substrate moving device 11 is movable between a position above the chip table 5 and a position retracted to the side thereof, and moves the held substrate 3 to an arbitrary position at the center position of the pressurizing table 5a of the chip table 5. When the substrate moving device 11 is in the retracted position, the substrate 3 is supplied by a substrate supply/takeout device (not shown) and the substrate 3 on which the chip 1 is mounted is taken out. It is configured as follows. Further, the back side of the substrate 3 of the substrate moving device 11 comes into contact with the support plate 11+z, and there are through holes 13 corresponding to the placement positions of the reference marks provided on the substrate and the chip mounting positions.
but! ? ! It is set up. 14 is the substrate moving device 11
A microscope 15 with a focus detection device equipped with a CCTV camera, an adhesive applicator 16 consisting of a dispenser that drips adhesive, and an ultraviolet irradiator 1 are installed on a workbench located above.
7 are arranged in parallel, and are configured to be movable in the Z-axis direction and movable in the arrangement direction of each of the above devices. The ultraviolet irradiation tool 17 includes a mercury lamp i4 having a shutter:
Ultraviolet rays are guided from 18 through a light 7 eyeper 19.
また、前記焦点検出装置付顕微鏡15は、前記作業台1
4に対してZ軸方向に移動可能な可動台20に取付けら
れている。Further, the microscope 15 with a focus detection device is arranged on the workbench 1.
It is attached to a movable base 20 that is movable in the Z-axis direction with respect to 4.
前記可動台20および焦点検出装置付顕微鏡15は、第
6図に示すように構成されている。照明装ra21によ
り照明されたチップ1の上面や基板3のチップ装着面の
標ah4の像は対物レンズ22によりCCTVカメラ2
3の撮像管上に結ばれるが、途中その光の一部はビーム
スプリッタ−24によって横方向に取り出され、さらに
ビームスプリッタ−と全反射プリズムの組み合わせ25
により直進光と、より長い光路の光束としてCCDライ
ンセンサー26上に2つの像を結ぶ、27は焦点判定装
置であり、CCDラインセンサー26上の2つの像のコ
ントラスト差から焦点位置方向を判定し、モータドライ
バー28によりモータ29を駆動し、ボールねじ30に
より可動台20を移動駆動する。この可動台20の高さ
位置は変位検出器31とカウンタ32により中央側m装
置(以下CPUと略す)にモニターされる。CCTVカ
メラ23の画像信号はカメラコントロールユニット33
を経てパターンマツチング方式位置読取装置34とモニ
ターテレビ35に送られ、位置読取り結果はCPUに伝
送される。The movable table 20 and the microscope 15 with a focus detection device are constructed as shown in FIG. The image of the mark ah4 on the top surface of the chip 1 and the chip mounting surface of the substrate 3 illuminated by the illumination device ra21 is captured by the CCTV camera 2 through the objective lens 22.
A part of the light is taken out laterally by a beam splitter 24, and then a combination of a beam splitter and a total reflection prism 25.
27 is a focus determination device that determines the focus position direction from the contrast difference between the two images on the CCD line sensor 26. , a motor 29 is driven by a motor driver 28, and a ball screw 30 drives a movable base 20 to move. The height position of the movable base 20 is monitored by a displacement detector 31 and a counter 32 by a central device (hereinafter abbreviated as CPU). The image signal of the CCTV camera 23 is sent to the camera control unit 33.
The position reading result is then sent to the pattern matching type position reading device 34 and the monitor television 35, and the position reading result is transmitted to the CPU.
以上の構成において、チップ1を基板3の所定位置に装
着する動作を$1図及び第2図により説明する。まず、
予め退避位置に移動した基板移動装置11に対して図示
しない基板供給取出装置にて基板3を供給し、またチッ
プテーブル5の加圧台5a上に図示しない移送装置にで
チップ1を移載して保持する1次に、基板移動!!置1
1をチップテーブル5の上方位置に移動させるとともに
、作業台14を所定位置まで下降させ、その後第1図(
a)に示すように、基板3に設けられた3つの基準標識
を順次焦点検出装置付顕微fi15の直下位置に位置決
めするとともに可動台20を移動させて自動焦点合せ動
作を行わせ、合焦点時の可動台20の高さ位置を変位検
出器31とカウンタ32によって読み取って、基板3の
3点のそれぞれの高さを検出する。これによりで基板3
のチップ装着面の位置及び傾きを検出することができる
。In the above configuration, the operation of mounting the chip 1 at a predetermined position on the substrate 3 will be explained with reference to FIG. 1 and FIG. first,
A substrate supply/takeout device (not shown) supplies the substrate 3 to the substrate moving device 11 which has been moved to the retracted position in advance, and a chip 1 is transferred onto the pressure table 5a of the chip table 5 by a transfer device (not shown). First, move the board! ! Place 1
1 to a position above the chip table 5, and lower the workbench 14 to a predetermined position.
As shown in a), the three reference marks provided on the substrate 3 are sequentially positioned directly below the microscope fi 15 with a focus detection device, and the movable table 20 is moved to perform an automatic focusing operation, and when the focus point is The height position of the movable base 20 is read by the displacement detector 31 and the counter 32, and the height of each of the three points on the board 3 is detected. This allows board 3
The position and inclination of the chip mounting surface can be detected.
次に、基板移動装W111を退避位置に移動させた後、
第1図(b)に示すように、作業台14を所定位置まで
さらに下降させ、チップテーブル5上のチップ1を焦点
検出装置付顕微fi15の視野に収め、その画像からチ
ップ1の位置を検出してXテーブル6、Yテーブル7、
θテーブル8を作動させ、チップ1の中心を所定位置に
位置決めし、次いでチップ1の上面の3.αを順次焦点
検出装置付顕微鏡15の直下位置に位置決めするととも
に可動台20を移動させて自動焦点動作を行わせ、合焦
点時の可動台20の高さ位置を上記と同様に読み取り、
チップ1の上面の3点の高さを検出し、チップ1の上面
位置と傾きを検出する。次いで、上記検出結果から、前
記基板3のチップ装着面に対してチップ1の上面が平行
となるように平行調整テーブル10を作動させる0次に
、第1図(c)に示すように、作業台14を横移動させ
てチップ1上に接着剤塗布@f116を対向位置させ、
接着剤36を吐出することによりで、第3図(a)に示
すように、チップ1の上面に接着剤36を塗布する。続
いて、作業台14を上昇させた後、基板移動装置11を
チップテーブル5の上方位置まで移動させてチップ1を
接合すべき位置をチップ1の直上に対向位置させ、Zテ
ーブル9を上昇動作させることによって、第1図(d)
及び第3図(b)に示すように、チップ1を基板3に対
して加圧し、チップ1のバンブ接点2を基板3のリード
4に圧接させる。このとき、各バンブ接点2は例えば1
辺が0.1mm程度と一般に小さいため、第4図に示す
ように、加圧力によってバンブ接点2とリード4の間か
ら接着剤36が完全に排除されるとともにバンプ接点2
がリード4表面に食い込むようにかつ弾性的に圧接され
、電気的接続が確保される。これと同時に作業台14が
横移動して紫外線照射共17がチップ1の直上に対向位
置するとともに作業台14が下降し、第1図(e)に示
すように紫外線照射共17から基板3の貫通孔13及び
透明な基板3を通して接着剤36に紫外線を照射してこ
れを硬化させ、チップ1を基板3に固定する。この間、
前記バンブ接点2とリード4の圧接状態を維持しておく
ことによって、接着剤36が硬化すると、チップ1の加
圧を解除しても上記圧接状態は保持され、バンブ接点2
とリード4の電気的接続が確実に保持されるのである。Next, after moving the substrate moving device W111 to the retreat position,
As shown in FIG. 1(b), the workbench 14 is further lowered to a predetermined position, the chip 1 on the chip table 5 is placed in the field of view of the microscope fi 15 with a focus detection device, and the position of the chip 1 is detected from the image. Then, set X table 6, Y table 7,
The θ table 8 is operated, the center of the chip 1 is positioned at a predetermined position, and then 3. α is sequentially positioned directly below the microscope 15 with a focus detection device, and the movable base 20 is moved to perform an automatic focusing operation, and the height position of the movable base 20 at the time of focusing is read in the same manner as above,
The heights of three points on the top surface of the chip 1 are detected, and the top surface position and inclination of the chip 1 are detected. Next, based on the above detection results, the parallel adjustment table 10 is operated so that the top surface of the chip 1 is parallel to the chip mounting surface of the substrate 3. Next, as shown in FIG. Move the stand 14 laterally to position the adhesive coating @f116 on the chip 1,
By discharging the adhesive 36, the adhesive 36 is applied to the upper surface of the chip 1, as shown in FIG. 3(a). Subsequently, after raising the workbench 14, the substrate moving device 11 is moved to a position above the chip table 5, the position where the chip 1 is to be bonded is positioned directly above the chip 1, and the Z table 9 is moved up. Figure 1(d)
As shown in FIG. 3(b), the chip 1 is pressed against the substrate 3, and the bump contacts 2 of the chip 1 are brought into pressure contact with the leads 4 of the substrate 3. At this time, each bump contact 2 has, for example, 1
Since the sides are generally small, about 0.1 mm, the adhesive 36 is completely removed from between the bump contact 2 and the lead 4 by the pressurizing force, and the bump contact
is pressed against the surface of the lead 4 so as to bite into it and elastically, thereby ensuring electrical connection. At the same time, the workbench 14 moves laterally so that the ultraviolet ray irradiator 17 is located directly above the chip 1, and the workbench 14 is lowered, and as shown in FIG. The adhesive 36 is irradiated with ultraviolet rays through the through hole 13 and the transparent substrate 3 to cure it, and the chip 1 is fixed to the substrate 3. During this time,
By maintaining the pressure contact state between the bump contact 2 and the lead 4, when the adhesive 36 hardens, the pressure contact state is maintained even when the pressure on the chip 1 is released, and the bump contact 2
The electrical connection between the lead 4 and the lead 4 is reliably maintained.
こうして、1つのチップ1の接合が完了すると、基板移
動装置!11が退避し、以降順次新たなチップ1がチッ
プテーブル5の加圧台5a上に移載され、上記と同様に
基板3に装着固定され、すべてのチップ1が!!装着固
定れると基板移動装置11が退避位置に退避して基板供
給取出装置にて取り出されるとともに、新たな基板3が
供給され、上記動作が繰り返されるのである。In this way, when the bonding of one chip 1 is completed, the substrate moving device! 11 is evacuated, and thereafter, new chips 1 are sequentially transferred onto the pressurizing table 5a of the chip table 5, and mounted and fixed on the substrate 3 in the same manner as above, and all the chips 1 are removed! ! When the substrate is fixed, the substrate moving device 11 retreats to the retracted position and is taken out by the substrate supply/takeout device, and a new substrate 3 is supplied, and the above operation is repeated.
尚、上記実施例では基板3及びチップ1の3点位置を検
出して平行調整を行ったが、基板3に基準面としての信
頼性がある場合はチップ1のみ3点位置を検出して平行
調整してもよく、さらに両者の平行度が亮い場合や、加
圧台5aに球面軸受等が内蔵されていて基板3に対して
平行調整機能を有している場合には平行調整工程を省略
することもできる。又、接着剤はチップ111でなく、
基板3側に塗布してもよい。さらに、上記実施例では基
板3として透明な基板を用いた例を示したが、基板3の
3点位置の検出及V紫外線照射をチップ装着面側から行
うようにすれば、不透明な基板にも適用可能である。In the above embodiment, the three-point positions of the substrate 3 and the chip 1 were detected to perform parallel adjustment, but if the substrate 3 is reliable as a reference surface, the three-point positions of the chip 1 alone are detected and parallel adjustment is performed. Further, if the parallelism between the two is high, or if the pressure table 5a has a built-in spherical bearing or the like and has a parallel adjustment function with respect to the substrate 3, the parallel adjustment process is performed. It can also be omitted. Also, the adhesive is not the chip 111,
It may also be applied to the substrate 3 side. Furthermore, in the above embodiment, a transparent substrate is used as the substrate 3, but if the detection of three points on the substrate 3 and the V ultraviolet ray irradiation are performed from the chip mounting surface side, even an opaque substrate can be used. Applicable.
発明の効果
本発明のチップの接合方法によれば、以上のようにバン
ブ接点を有するチップを基板に接着剤を用いて接合しで
おり、熱や超音波を印加する必要がないので、装置が簡
単になるとともに容易かっ確実にチップを基板に固定す
ることができ、しかもバンブ接点をリードに圧接して電
気的接続を確保した状態でそのまま接着剤を硬化させて
接合しているので、接着剤の硬化による機械的接合完了
後、加圧を解除してもバンブ接5αはその弾性復元力に
よってリードに圧接されて電気的接続が保持され、機械
的並びに電気的接合を確実に得ることができる。Effects of the Invention According to the chip bonding method of the present invention, a chip having a bump contact is bonded to a substrate using an adhesive as described above, and there is no need to apply heat or ultrasonic waves, so the device can be easily It is easy to fix the chip to the board easily and reliably, and since the bump contacts are pressed against the leads and the electrical connection is secured, the adhesive is cured and bonded. After completion of mechanical bonding due to hardening, even if the pressure is removed, the bump contact 5α is pressed against the lead due to its elastic restoring force and the electrical connection is maintained, making it possible to reliably obtain mechanical and electrical bonding. .
また、第2発明ではチップと基板の加圧時にそれらの平
行ml!!を行っているので、すべての接合面が確実に
圧接して信頼性の高い電気的接合状態を得ることができ
る等、大なる効果を発揮する。Moreover, in the second invention, when the chip and the substrate are pressed, their parallel ml! ! Because this process is carried out, all bonding surfaces are securely pressed against each other and a highly reliable electrical bonding state can be obtained, resulting in great effects.
着剤の塗布状態及びチップの圧接状態の拡大正面図、第
4図はバンブ接点とリードの圧接状態を示す拡大断面図
、15図は接合装置の全体概略構成を示す部分断面正面
図、第6図は焦点検出装置付顕微鏡の構成原理図、第7
図は従来装置の概略構成を示す正面図である。
1・・・・・・・・・チップ
2・・・・・・・・・バンプ接、嶽
3・・・・・・・・・基板
4・・・・・・・・・リード
5・・・・・・・・・チップテーブル
5a・・・・・・加圧台
10・・・・・・・・・平行調整テーブル15・・・・
・・・・・焦点検出装置付顕徴競16・・・・・・・・
・接着剤塗布装置17・・・・・・・・・紫外線照射共
。
代理人f)酩弁理士 中尾敏男 はか1名第1図
1−−−デツプ 4−−−リード
10−−一乎行調整デーフンレ2−−−ペンブ棲矛、
5−一−ヂ・ノフ’t−n7/ 1s −−
−4、市、劃【≧1に置村到晴鮫鏡3−4−破51−%
L台16−1着@6技ff117−キ/+緑閉、e其
第2図
第3図 第4図
第5図
填 6 図
第7図FIG. 4 is an enlarged sectional view showing the state in which the adhesive is applied and the chip is in pressure contact; FIG. 4 is an enlarged sectional view showing the state in which the bump contact and the lead are in pressure contact; FIG. The figure is a diagram of the configuration principle of a microscope with a focus detection device.
The figure is a front view showing a schematic configuration of a conventional device. 1... Chip 2... Bump contact, Mount 3... Board 4... Lead 5... ...... Chip table 5a... Pressure table 10... Parallel adjustment table 15...
... Focus detection device 16...
・Adhesive coating device 17......Ultraviolet irradiation. Agent f) Drunk patent attorney Toshio Nakao (1 person) Figure 1 1 --- Dep 4 --- Lead
10--Ichigo Adjustment Defunle 2---Pembu Suiko,
5-1-di nofu't-n7/ 1s --
-4, Ichi, Hara [≧1 to Haru Okimura Samekagami 3-4-break 51-%
L stand 16-1 arrival @ 6 technique ff 117-ki/+ green closed, e fig. 2 fig. 3 fig. 4 fig. 5 fill 6 fig. fig. 7
Claims (4)
のチップ接合面に紫外線硬化型の接着剤を塗布する工程
と、チップのバンプ接点を基板のリードに圧接させるよ
うにチップと基板を加圧する工程と、この加圧状態で前
記接着剤に紫外線を照射して接着剤を硬化させ、バンプ
接点とリードを圧接させて電気的に接続した状態でチッ
プを基板に固定する工程とを備えていることを特徴とす
るチップの接合方法。(1) A step of applying an ultraviolet curable adhesive to one side of the chip on which bump contacts are formed or the chip bonding surface of the substrate, and then applying pressure to the chip and the substrate so that the bump contacts of the chip come into pressure contact with the leads of the substrate. and a step of curing the adhesive by irradiating the adhesive with ultraviolet rays in this pressurized state, and fixing the chip to the substrate with the bump contacts and the leads in pressure contact and electrically connected. A chip joining method characterized by:
チップ接合面との平行調整を行う工程と、チップの一側
面又は基板のチップ接合面に紫外線硬化型の接着剤を塗
布する工程と、チップのバンプ接点を基板のリードに圧
接させるようにチップと基板を加圧する工程と、この加
圧状態で前記接着剤に紫外線を照射して接着剤を硬化さ
せ、バンプ接点とリードを圧接させて電気的に接続した
状態でチップを基板に固定する工程とを備えていること
を特徴とするチップの接合方法。(2) A step of adjusting parallelism between one side of the chip on which a bump contact is formed and the chip bonding surface of the substrate, and a step of applying an ultraviolet curing adhesive to one side of the chip or the chip bonding surface of the substrate. , a step of pressurizing the chip and the substrate so that the bump contacts of the chip are brought into pressure contact with the leads of the board, and in this pressurized state, the adhesive is irradiated with ultraviolet rays to harden the adhesive, and the bump contacts and the leads are brought into pressure contact. and fixing the chip to a substrate in an electrically connected state.
を、チップの一側面の3点を検出して行う特許請求の範
囲第2項に記載のチップの接合方法。(3) The chip bonding method according to claim 2, wherein the parallel adjustment between one side of the chip and the chip bonding surface of the substrate is performed by detecting three points on one side of the chip.
を、チップの一側面と基板のチップ接合面の各3点を検
出して行う特許請求の範囲第2項に記載のチップの接合
方法。(4) The chip bonding according to claim 2, in which the parallel adjustment between one side of the chip and the chip bonding surface of the substrate is performed by detecting three points each on the one side of the chip and the chip bonding surface of the substrate. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61273280A JPS63127541A (en) | 1986-11-17 | 1986-11-17 | Method of bonding chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61273280A JPS63127541A (en) | 1986-11-17 | 1986-11-17 | Method of bonding chip |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63127541A true JPS63127541A (en) | 1988-05-31 |
JPH0482184B2 JPH0482184B2 (en) | 1992-12-25 |
Family
ID=17525645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61273280A Granted JPS63127541A (en) | 1986-11-17 | 1986-11-17 | Method of bonding chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63127541A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02234447A (en) * | 1989-03-07 | 1990-09-17 | Nec Corp | Method of connection semiconductor integrated circuit element |
US5037780A (en) * | 1989-02-02 | 1991-08-06 | Matsushita Electric Industrial Co., Ltd. | Method for attaching semiconductors to a transparent substrate using a light-curable resin |
US5766972A (en) * | 1994-06-02 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Method of making resin encapsulated semiconductor device with bump electrodes |
JP2005028202A (en) * | 2003-07-07 | 2005-02-03 | Hitachi Industries Co Ltd | Table parallelism adjusting device and dispenser using the same |
JP2009030270A (en) * | 2007-07-25 | 2009-02-12 | Panasonic Electric Works Co Ltd | Flooring material |
JP2010034585A (en) * | 2009-11-06 | 2010-02-12 | Toray Eng Co Ltd | Method for adjusting parallelism in chip mounting device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1986
- 1986-11-17 JP JP61273280A patent/JPS63127541A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60262430A (en) * | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5037780A (en) * | 1989-02-02 | 1991-08-06 | Matsushita Electric Industrial Co., Ltd. | Method for attaching semiconductors to a transparent substrate using a light-curable resin |
JPH02234447A (en) * | 1989-03-07 | 1990-09-17 | Nec Corp | Method of connection semiconductor integrated circuit element |
US5766972A (en) * | 1994-06-02 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Method of making resin encapsulated semiconductor device with bump electrodes |
JP2005028202A (en) * | 2003-07-07 | 2005-02-03 | Hitachi Industries Co Ltd | Table parallelism adjusting device and dispenser using the same |
JP2009030270A (en) * | 2007-07-25 | 2009-02-12 | Panasonic Electric Works Co Ltd | Flooring material |
JP2010034585A (en) * | 2009-11-06 | 2010-02-12 | Toray Eng Co Ltd | Method for adjusting parallelism in chip mounting device |
Also Published As
Publication number | Publication date |
---|---|
JPH0482184B2 (en) | 1992-12-25 |
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