JPS63124411A - Nanufacture of semiconductor device - Google Patents
Nanufacture of semiconductor deviceInfo
- Publication number
- JPS63124411A JPS63124411A JP27009986A JP27009986A JPS63124411A JP S63124411 A JPS63124411 A JP S63124411A JP 27009986 A JP27009986 A JP 27009986A JP 27009986 A JP27009986 A JP 27009986A JP S63124411 A JPS63124411 A JP S63124411A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitride
- barrier layer
- semiconductor device
- plasma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 33
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 14
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 238000004544 sputter deposition Methods 0.000 claims abstract description 12
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 9
- 239000000956 alloy Substances 0.000 claims abstract description 9
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 9
- 239000003870 refractory metal Substances 0.000 claims abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001301 oxygen Substances 0.000 claims abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 7
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 19
- 229910052782 aluminium Inorganic materials 0.000 claims description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 13
- 230000000694 effects Effects 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 229910001080 W alloy Inorganic materials 0.000 abstract description 9
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 abstract description 9
- -1 hafnium nitride Chemical class 0.000 abstract description 8
- 229910052735 hafnium Inorganic materials 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 150000002500 ions Chemical class 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 238000000059 patterning Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000002648 laminated material Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910001069 Ti alloy Inorganic materials 0.000 description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 239000010937 tungsten Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の製造方法の改良である。特に、金属電極・
配線のバリヤ層のバリヤ効果を向上する改良である。DETAILED DESCRIPTION OF THE INVENTION [Summary] This is an improvement in a method for manufacturing a semiconductor device. In particular, metal electrodes
This is an improvement that improves the barrier effect of the interconnect barrier layer.
シリコン上にアルミニウム電極が形成されてなる半導体
装置のアルミニウム電極の下面に形成されるバリヤ層の
形成に、窒化チタン、窒化ハブニュウム、窒化ジルコニ
ウム、チタンとタングステンとの合金等リフラクトリメ
タルの窒化物等の焼結合金をターゲットとするスパッタ
リング法を使用するものである。Refractory metal nitrides such as titanium nitride, hubium nitride, zirconium nitride, and alloys of titanium and tungsten are used to form a barrier layer formed on the lower surface of an aluminum electrode in a semiconductor device in which an aluminum electrode is formed on silicon. This method uses a sputtering method that targets a sintered alloy.
半導体装置の製造方法の改良に関する。特に、バリヤ層
のバリヤ効果を向上することのできる金属電極・配線の
製造方法の改良に関する。This invention relates to improvements in methods for manufacturing semiconductor devices. In particular, the present invention relates to improvements in methods for manufacturing metal electrodes and interconnections that can improve the barrier effect of barrier layers.
シリコン基板を使用して製造される半導体装置の金属電
極の材料にはアルミニウムが使用される場合が多いが、
■族の金属であるアルミニウムはシリコン中に拡散する
とｐ型の不純物として機能し、さらに、シリコン基板に
形成されているｐ−ｎ接合が浅いときはスパイクとなっ
てｐ−ｎ接合を破壊する。Aluminum is often used as the material for metal electrodes in semiconductor devices manufactured using silicon substrates.
Aluminum, which is a group metal, functions as a p-type impurity when diffused into silicon, and furthermore, when the p-n junction formed in the silicon substrate is shallow, it becomes a spike and destroys the p-n junction.
そのため、従来、リフラクトリメタルの窒化物、窒化ハ
フニュウム、窒化ジルコニウム、チタンとタングステン
との合金等よりなるノくリヤ層をもってアルミニウムと
シリコンとを隔離することがなされており、特に、浅い
エミッタをイオン注入法を使用して形成するときは、注
入イオンに対する保護膜としての多結晶シリコン膜も必
要であり、さらに、バリヤ層との接触を良好にするため
にアルミニウム膜を多結晶シリコン膜とｌくリヤ層との
間に介在させることも必要である等の理由により、第５
図に示す構造とされており、以下のようにして製造され
ていた。Therefore, conventionally, aluminum and silicon are separated by a layer made of refractory metal nitride, hafnium nitride, zirconium nitride, alloy of titanium and tungsten, etc., and in particular, shallow emitters are When forming using the implantation method, a polycrystalline silicon film is also required as a protective film against implanted ions, and in addition, an aluminum film is mixed with the polycrystalline silicon film to improve contact with the barrier layer. Due to reasons such as the need to interpose it between the rear layer and the
It has the structure shown in the figure and was manufactured as follows.
第５図参照
シリコン基板１上に形成された二酸化シリコン等の絶縁
膜２に電極コンタクト用開口を形成し、注入イオンに対
する保護膜として多結晶シリコン膜４を厚さ １．００
０人に形成した後、イオン注入をなしてエミッタ領域等
５を形成し、コンタクト層としてのチタン膜またはアル
ミニウム膜を厚さ１００〜５００人に形成し、窒化チタ
ン、窒化ハフニュウム、窒化ジルコニウム、チタンとタ
ングステンとの合金等のバリヤ層を厚さ １，２００人
に形成し、電極主材としてのアルミニウム膜を形成し、
これをパターニングして電極舎配線９を形成する。Refer to FIG. 5. An electrode contact opening is formed in an insulating film 2 made of silicon dioxide or the like formed on a silicon substrate 1, and a polycrystalline silicon film 4 is formed to a thickness of 1.00 mm as a protective film against implanted ions.
After forming the 0 layer, ion implantation is performed to form the emitter region 5, and a titanium film or aluminum film as a contact layer is formed to a thickness of 100 to 500 layers. A barrier layer such as an alloy of
This is patterned to form the electrode housing wiring 9.
上記せる従来技術の金属電極・配線をもってしてはバリ
ヤ層の効果が十分ではなく、アルミニウムとシリコンと
がバリヤ層を貫通して相互に拡散し、シリコン基板中に
かなりの量のアルミニウムが混入する欠点がある。With the metal electrodes and wiring of the prior art described above, the effect of the barrier layer is not sufficient, and aluminum and silicon penetrate through the barrier layer and diffuse into each other, resulting in a considerable amount of aluminum being mixed into the silicon substrate. There are drawbacks.
本発明の目的は、この欠点を解消することにあり、バリ
ヤ効果のすぐれた金属電極を有する半導体装置の製造方
法を提供することにある。An object of the present invention is to eliminate this drawback, and to provide a method for manufacturing a semiconductor device having a metal electrode with an excellent barrier effect.
上記の目的を達成するために本発明が採った手段は、バ
リヤ層としてのりフラクトリメタルの窒化物等（窒化チ
タン、窒化ハフニュウム、窒化ジルコニウム、チタンと
タングステンとの合金等）の膜を、リフラクトリメタル
の窒化物等（窒化チタン、窒化ハフニュウム、窒化ジル
コニウム、チタンとタングステンとの合金等）の焼結合
金をターゲットとしてなすスパッタリング法を使用して
形成することにある。The means taken by the present invention to achieve the above object is to use a reflux metal nitride film (titanium nitride, hafnium nitride, zirconium nitride, alloy of titanium and tungsten, etc.) as a barrier layer. It is formed using a sputtering method using a sintered alloy of trimetal nitride (titanium nitride, hafnium nitride, zirconium nitride, alloy of titanium and tungsten, etc.) as a target.
さらに、上記のようにして形成したバリヤ層に熱処理を
施し、または、酸素ガス、アンモニヤプラズマ、窒素プ
ラズマ、または、酸素プラズマ等に接触すると、バリヤ
効果はさらに向上する。Further, when the barrier layer formed as described above is subjected to heat treatment or brought into contact with oxygen gas, ammonia plasma, nitrogen plasma, oxygen plasma, etc., the barrier effect is further improved.
バリヤ層として使用しうる材料の選択範囲は）ある程度
限定されているので、その形成方法を種々に変化させて
実験をなした。Since the selection range of materials that can be used as the barrier layer is somewhat limited, experiments were conducted with various methods of forming the barrier layer.
その結果、窒化チタン、窒化ハフニュウム、窒化ジルコ
ニウム、チタンとタングステンとの合金等の焼結合金を
ターゲットとしてなすスパッタリング法を使用するとバ
リヤ効果のすぐれた窒化チタン等の膜を形成することが
でき、さらに、これに、酸素雰囲気を接触させたり、４
８０℃の窒素中で約３０分間熱処理したり、アンモニヤ
プラズマ、窒素プラズマ、酸素プラズマ等に接触させる
と、バリヤ効果がさらに向上することができることが確
認された。As a result, by using a sputtering method using a sintered alloy such as titanium nitride, hafnium nitride, zirconium nitride, or an alloy of titanium and tungsten as a target, it is possible to form a film such as titanium nitride with an excellent barrier effect. , by contacting it with an oxygen atmosphere, or by
It has been confirmed that the barrier effect can be further improved by heat treatment in nitrogen at 80° C. for about 30 minutes or by contacting with ammonia plasma, nitrogen plasma, oxygen plasma, etc.
本発明は、この新たに発見された性質を利用するもので
ある。The present invention takes advantage of this newly discovered property.
以下、図面を参照しつへ、本発明の一実施例に係るダイ
オードの製造方法についてさらに説明する。Hereinafter, a method for manufacturing a diode according to an embodiment of the present invention will be further described with reference to the drawings.
第２図参照
一導電型のシリコン基板１に二酸化シリコン等の絶縁膜
２を形成し、これに電極コンタクト用開口３を形成し、
注入イオンに対する保護膜としての多結晶シリコン膜４
を厚さ ｔ、ｏｏｏ八に形成する。この多結晶シリコン
膜４を貫通して反対導電型の不純物をイオン注入してｐ
−ｎ接合５１を形成する。Refer to FIG. 2. An insulating film 2 such as silicon dioxide is formed on a silicon substrate 1 of one conductivity type, and an electrode contact opening 3 is formed therein.
Polycrystalline silicon film 4 as a protective film against implanted ions
is formed to a thickness of t, ooo 8. By penetrating this polycrystalline silicon film 4 and implanting impurity ions of the opposite conductivity type, p
-N junction 51 is formed.
次に、コンタ、クト層としてのチタン膜またはアルミニ
ウム膜６を厚さ １００〜５００人に形成する。Next, a titanium film or aluminum film 6 as a contact layer is formed to a thickness of 100 to 500 mm.
第３図参照
次に窒化チタン等のバリヤ層７を厚さ １，２００人に
形成するが、図示するようなスパッタ装置を使用する。Referring to FIG. 3, a barrier layer 7 of titanium nitride or the like is then formed to a thickness of 1,200 mm using a sputtering apparatus as shown.
図において、１０はスパッタ用真空容器であり、真空ポ
ンプ１１をもって１Ｏ−３Ｔｏｒｒに排気されることが
できる。ここに、アルゴンと窒素との混合ガスを供給し
て内圧を１Ｏ−７Ｔｏｒｒに保つ。１２はウェーハホル
ダであり、半導体ウェーハ１３が乗せられ、正電位が与
えられる。１４はターゲットであり、負電位が与えられ
る。In the figure, 10 is a vacuum vessel for sputtering, which can be evacuated to 10-3 Torr using a vacuum pump 11. A mixed gas of argon and nitrogen is supplied here to maintain the internal pressure at 10-7 Torr. Reference numeral 12 denotes a wafer holder, on which a semiconductor wafer 13 is placed and a positive potential is applied. 14 is a target to which a negative potential is applied.
第４図参照
ここで、ターゲットとして、窒化チタン、窒化ハフニュ
ウム、窒化ジルコニウム、チタンとタングステンとの合
金等の中から選択された材料の焼結合金を使用し、アル
ゴンと窒素との混合ガスを反応ガスとして、スパッタを
なす。Refer to Figure 4 Here, a sintered alloy of material selected from titanium nitride, hafnium nitride, zirconium nitride, alloy of titanium and tungsten, etc. is used as a target, and a mixed gas of argon and nitrogen is reacted. Spatters as a gas.
このようにして、窒化チタン、窒化ハフニュウム、窒化
ジルコニウム、チタンとタングステンとの合金等よりな
り厚さが１，２００人のバリヤ層７を形成した後、電極
主材としてのアルミニウム膜８を形成する。または、バ
リヤ層７を形成した後、酸素ガス、アンモニヤプラズマ
、窒素プラズマ、または、・酸素プラズマ等に低触させ
たり、窒素ガス中において熱処理を施した後、アルミニ
ウム膜８を形成する。In this way, after forming a barrier layer 7 of 1,200 nm thick made of titanium nitride, hafnium nitride, zirconium nitride, an alloy of titanium and tungsten, etc., an aluminum film 8 as the main material of the electrode is formed. . Alternatively, after forming the barrier layer 7, the aluminum film 8 is formed after being exposed to oxygen gas, ammonia plasma, nitrogen plasma, oxygen plasma, etc., or heat-treated in nitrogen gas.
第１図参照
上記の積層体をバターニングして電極・配線９を形成す
る。Refer to FIG. 1. Electrodes/wirings 9 are formed by patterning the above laminate.
以上の工程をもって製造された金属電極は、その結晶の
品質が極めて優れており、そのバリヤ効果は極めてすぐ
れている。The metal electrode manufactured through the above process has extremely excellent crystal quality and has an extremely excellent barrier effect.
以上説明せるとおり、本発明に係る半導体装置の製造方
法においては、バリヤ層としてのりフラクトリメタルの
窒化物等（窒化チタン、窒化／＼フニュウム、窒化ジル
コニウム、チタンとタングステンとの合金等）の膜を、
リフラクトリメタルの窒化物等（窒化チタン、窒化）＼
フニュウム、窒化ジルコニウム、チタンとタングステン
との合金等）の焼結合金をターゲットとしてなすスノく
ツタリング法を使用して形成されているので、いるので
、この結晶の品質は極めて優れており、このバリヤ層の
バリヤ効果は極めてすぐれている。また、焼結合金をタ
ーゲットとしてスノくツタリング法で成膜したバリヤ層
を酸素ガス、アンモニヤプラズマ、窒素プラズマ、また
は、酸素プラズマ等に低触させたり、窒素ガス中におｌ
、％て−Ｅ
熱処理を施したりすることでバリヤ効果はさらに向上す
る。As explained above, in the method for manufacturing a semiconductor device according to the present invention, a film of a frac metal nitride or the like (titanium nitride, nitride/Funium, zirconium nitride, alloy of titanium and tungsten, etc.) is used as a barrier layer. of,
Refractory metal nitrides, etc. (titanium nitride, nitride)
The quality of this crystal is extremely excellent, and this barrier The barrier effect of the layer is extremely good. In addition, the barrier layer formed using the sintered alloy as a target by the snoki tuttering method may be brought into low contact with oxygen gas, ammonia plasma, nitrogen plasma, or oxygen plasma, or immersed in nitrogen gas.
, % -E The barrier effect can be further improved by heat treatment.
第１図は、本発明の一実施例に係る半導体装置の製造方
法を実施して製造したダイオードの断面図である。
第２図は、本発明の一実施例に係る半導体装置の製造方
法の工程図である。
第３図は、本発明の実施に使用されるスパッタ装置の構
造図である。
第４図は、本発明の一実施例に係る半導体装置の製造方
法の工程図である。
第５図は、従来技術に係る半導体装置の製造方法を説明
する図である。
１・・・シリコン基板、
２・・・絶縁膜、
３・・・電極コンタクト用開口、
４・・・多結晶シリコン膜、
５・・・エミッタ領域、
：２−
６・・・金属膜（コンタクト層）、
７・・・バリヤ層。
８・・・電極会配線膜、
９・φ・電極・配線、
１０・・・スパッタ用真空容器、
１１−・・真空ポンプ、
１２・・拳ウェーハホルダ、
１３・・・半導体ウェーハ、
１４・・・ターゲット。
工程図
第 ４ 図
本発明
第１Ｉ！FIG. 1 is a cross-sectional view of a diode manufactured by implementing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a structural diagram of a sputtering apparatus used to implement the present invention. FIG. 4 is a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a method of manufacturing a semiconductor device according to the prior art. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Insulating film, 3... Opening for electrode contact, 4... Polycrystalline silicon film, 5... Emitter region, : 2- 6... Metal film (contact) layer), 7...barrier layer. 8... Electrode assembly wiring film, 9... Electrode/wiring, 10... Vacuum vessel for sputtering, 11-... Vacuum pump, 12... Fist wafer holder, 13... Semiconductor wafer, 14... ·target. Process diagram Figure 4 Invention No. 1I!
Claims (1)
ルの窒化物等の膜（７）よりなるバリヤ層が設けられて
なる金属電極・配線（９）を有する半導体装置の製造方
法において、 前記リフラクトリメタルの窒化物等の膜（７）の形成に
は、リフラクトリメタルの窒化物等の焼結合金をターゲ
ットとしてなすスパッタリング法を使用することを特徴
とする半導体装置の製造方法。 ［２］前記スパッタ法を使用して前記バリヤ層を形成し
た後、酸素ガス、アンモニヤプラズマ、窒素プラズマ、
または、酸素プラズマに接触させることを特徴とする特
許請求の範囲第１項記載の半導体装置の製造方法。 ［３］前記スパッタ法を使用して前記バリヤ層を形成し
た後、窒素ガス中において熱処理を施すことを特徴とす
る特許請求の範囲第１項記載の半導体装置の製造方法。[Claims] [1] A semiconductor device having a metal electrode/wiring (9) in which a barrier layer made of a refractory metal nitride film (7) is provided on the lower surface of an aluminum film (8). In the manufacturing method of the semiconductor device, the film (7) of refractory metal nitride or the like is formed using a sputtering method using a sintered alloy such as refractory metal nitride as a target. Production method. [2] After forming the barrier layer using the sputtering method, oxygen gas, ammonia plasma, nitrogen plasma,
The method for manufacturing a semiconductor device according to claim 1, further comprising bringing the semiconductor device into contact with oxygen plasma. [3] The method for manufacturing a semiconductor device according to claim 1, wherein after forming the barrier layer using the sputtering method, heat treatment is performed in nitrogen gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27009986A JPS63124411A (en) | 1986-11-13 | 1986-11-13 | Nanufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27009986A JPS63124411A (en) | 1986-11-13 | 1986-11-13 | Nanufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63124411A true JPS63124411A (en) | 1988-05-27 |
Family
ID=17481518
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27009986A Pending JPS63124411A (en) | 1986-11-13 | 1986-11-13 | Nanufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63124411A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877031A (en) * | 1994-07-07 | 1999-03-02 | Hyundai Electronics Industries Co, Ltd | Method for forming a metallic barrier layer in semiconductor device |
-
1986
- 1986-11-13 JP JP27009986A patent/JPS63124411A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5877031A (en) * | 1994-07-07 | 1999-03-02 | Hyundai Electronics Industries Co, Ltd | Method for forming a metallic barrier layer in semiconductor device |
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