JPS63240017A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63240017A JPS63240017A JP7465087A JP7465087A JPS63240017A JP S63240017 A JPS63240017 A JP S63240017A JP 7465087 A JP7465087 A JP 7465087A JP 7465087 A JP7465087 A JP 7465087A JP S63240017 A JPS63240017 A JP S63240017A
- Authority
- JP
- Japan
- Prior art keywords
- titanium
- film
- silicon
- silicon substrate
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000010936 titanium Substances 0.000 claims abstract description 12
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 12
- -1 argon ions Chemical class 0.000 claims abstract description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000004544 sputter deposition Methods 0.000 claims abstract description 7
- 229910052786 argon Inorganic materials 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 abstract description 7
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000001771 impaired effect Effects 0.000 abstract description 2
- 238000002156 mixing Methods 0.000 abstract description 2
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 8
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000005054 agglomeration Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関し、特に高集積度・
高速の半導体集積回路の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing semiconductor devices, particularly for highly integrated and
The present invention relates to a method for manufacturing a high-speed semiconductor integrated circuit.
従来の技術
半導体集積回路の高密度化に伴って構成要素であるＭＯ
Ｓ）ランジスタも縮小化されるが、かかる装置において
は深さ方向の縮小化も実施しなくては正常なトランジス
タ動作を維持することはできない。このことは高速動作
が可能でかつ接合リーク電流の少ないＭＯＳ）ランジス
タを構成することと相反する。Conventional technologyAs the density of semiconductor integrated circuits increases, MO, which is a component
S) Transistors are also being reduced in size, but in such a device, normal transistor operation cannot be maintained unless reduction in the depth direction is also performed. This contradicts the need to construct a MOS (MOS) transistor that is capable of high-speed operation and has low junction leakage current.
以上の問題を解決するために最近注目されているのがシ
リコンにおける不純物高濃度層より低抵抗な高融点金属
のシリサイド層を合金反応を用いてシリコン露出領域に
自己整合的に形成する技術（シリサイド化接合法）であ
る。但しこの方法では堆積された高融点金属と基板シリ
コンとのシリサイド化反応が均一に起こりにくいという
難点がある。これを解決するだめの方法として、高融点
金属を堆積した時点でシリコン基板との界面をミキシン
グするためドーパントであるヒ素イオンあるいは非ドー
パントであるシリコンイオンを界面近傍に注入したのち
シリサイド化のだめの熱処理を行うものが報告されてい
る。例えばアイ・イー拳イー・イー・トランザクシロン
オブ エレクトロン デバイスイズ ＥＤ−ａｌ（１
９８４年）第１３２９頁から第１３３４頁（ＩＥ３Ｔｒ
ａｎｓ ＥｌｅｃｔｒｏｎＤｅｖｉｃｅｓ ＥＤ−３１
（１９８４）ｐｐ１３２９−１３３４）。In order to solve the above problems, a technology that has recently attracted attention is to form a silicide layer of a refractory metal, which has a lower resistance than a high impurity concentration layer in silicon, in a self-aligned manner on the exposed silicon region using an alloy reaction. (chemical bonding method). However, this method has a drawback in that the silicidation reaction between the deposited high melting point metal and the silicon substrate is difficult to occur uniformly. As a solution to this problem, when the high melting point metal is deposited, in order to mix the interface with the silicon substrate, arsenic ions as a dopant or silicon ions as a non-dopant are implanted near the interface, and then heat treatment is performed to form a silicide. It has been reported that some people do this. For example, I-E-Fist E-E Transaxilon of Electron Devices ED-al (1
984) pages 1329 to 1334 (IE3Tr
ans ElectronDevices ED-31
(1984) pp1329-1334).
発明が解決しようとする問題点
拡散層上に合金反応により自己整合的にチタンシリサイ
ドを形成する技術においては、これを大規模集積回路に
適用する限り、チタンシリサイド膜形成後に為される熱
処理（ＶＡＩえば注入不純物の活性化や層間絶縁膜のフ
ローなど）を経ても膜の均一性が維持されることが必要
である。しかし現在までのところチタンシリサイド膜形
成時にはミキシング注入を用いることにより均一性の良
好な膜質が得られても、のちの比較的高温・長時間の熱
処理（９００°Ｃ以上、３０分間以上）の際にチタンシ
リサイドが凝集することによって表面粗れが生じシリサ
イドの亀裂部ではシリコン基板が露出するという問題が
あった。Problems to be Solved by the Invention In the technology of forming titanium silicide in a self-aligned manner by alloy reaction on the diffusion layer, as long as this is applied to large-scale integrated circuits, heat treatment (VAI) performed after the formation of the titanium silicide film is difficult. For example, it is necessary to maintain the uniformity of the film even after activation of implanted impurities, flow of an interlayer insulating film, etc.). However, to date, even though mixing injection has been used to form a titanium silicide film and a film with good uniformity has been obtained, it has been difficult to obtain a film with good uniformity when forming a titanium silicide film. There was a problem in that the agglomeration of titanium silicide caused surface roughness and exposed the silicon substrate at cracks in the silicide.
本発明はかかる点に鑑みてなされたもので、チタンシリ
サイド膜形成後に実用的な大規模集積回路製造上必要と
される熱処理を経てもシリサイド膜の均一性が維持され
るチタンシリサイド化接合を自己整合的に形成すること
を目的としている。The present invention has been made in view of the above points, and is a self-contained titanium silicide bond that maintains the uniformity of the silicide film even after the heat treatment required for practical large-scale integrated circuit manufacturing after the formation of the titanium silicide film. The purpose is to form them in a consistent manner.
問題点を解決するための手段
本発明は上記問題点を解決するため、シリコン基板表面
にアルゴンイオンによる逆スパッタリングを加えること
により、この基板表面上の自然酸化膜を除去するととも
にシリコンの活性面を露出させた直後同一真空槽内で金
属チタンを堆積することにより耐熱性に優れたチタンシ
リサイド層を形成するものである。Means for Solving the Problems In order to solve the above problems, the present invention applies reverse sputtering using argon ions to the surface of a silicon substrate to remove the natural oxide film on the surface of the substrate and to remove the active surface of silicon. By depositing metallic titanium in the same vacuum chamber immediately after exposure, a titanium silicide layer with excellent heat resistance is formed.
作 用
本発明は上記した方法により、たとえば９００°Ｃ２３
０分間以上の熱処理及びＣＨＦ３＋０゜系ドライエッチ
に対する耐性に優れ、かつ膜質の均一性が良好なチタン
シリサイド化接合を得ることができる。Function The present invention can be carried out by the method described above, for example, at 900°C23.
It is possible to obtain a titanium silicided bond that has excellent resistance to heat treatment for 0 minutes or more and CHF3+0° dry etching, and has good uniformity in film quality.
実施列
第１図〜第４図は本発明の一実施例のチタンシリサイド
化接合を形成する工程断面図である。第１図において、
１はシリコン基板（１０ｏ）で比抵抗はｎ型なら１〜１
．６Ω・ａｍ 、ｐ型なら１０−１．５Ω−偏とする。Embodiment FIGS. 1 to 4 are cross-sectional views of the process of forming a titanium silicided junction according to an embodiment of the present invention. In Figure 1,
1 is a silicon substrate (10o) and the resistivity is 1 to 1 if it is n type.
．． 6 Ω·am, 10-1.5 Ω- bias for p-type.
２は素子間分離用に形成された酸化膜である。このシリ
コン基板表面の自然酸化膜蚕除去するとともにシリコン
基板の活性面を露出させるため、アルゴンイオンによる
逆スパッタリングを行った。この時のスパッタ条件はア
ルゴンガス圧０．２５Ｐａ、ＲＦ投入電力２００Ｗ、ス
パッタ時間４分間でら９．５１０２膜が約７０人スパッ
タリングされる条件である。この直後同一真空槽内にお
いてシリコン基板全面に金属チタン被膜３をＤＣマグネ
トロンスパッタ法により３５ｎｍ堆積したあと、チタン
被膜とシリコン基板の界面をミキシングするためシリコ
ンイオン注入をエネルギー４０ ｋｅｙ 、ドーズ量６
×１０ｃＩＩ＆ の条件で行う（第２図）。2 is an oxide film formed for isolation between elements. In order to remove the natural oxide film on the surface of the silicon substrate and expose the active surface of the silicon substrate, reverse sputtering was performed using argon ions. The sputtering conditions at this time were argon gas pressure of 0.25 Pa, RF input power of 200 W, sputtering time of 4 minutes, and approximately 70 people sputtered 9.5102 films. Immediately after this, a metallic titanium film 3 of 35 nm was deposited on the entire surface of the silicon substrate in the same vacuum chamber by DC magnetron sputtering, and then silicon ions were implanted at an energy of 40 keys and a dose of 6 to mix the interface between the titanium film and the silicon substrate.
The test was carried out under the conditions of ×10cII& (Fig. 2).
次に窒素ガスの導入が可能なランプアニーラ−により６
００〜６５０’Ｃの温度範囲で６０秒間熱処理し、シリ
コン基板上のチタンのシリサイド化を行う。Ｈ２ｓ０４
＋−ρ２液により窒化チタンを選択的に除去したところ
、チタンシリサイドの分離酸化膜上への這い上がり（横
方向成長）がなく、シリコン上にのみチタンシリサイド
層４が形成される。さらにチタンシリサイド層４をダイ
シリサイド化するため窒素雰囲気中で７６０〜８００°
Ｃの温度範囲で再びランプアニールを行う。次にｎ＋ｐ
接合の形成のためにはドーズ量１０１５ ｃｍ−２台の
Ａｓ＋をエネルギー８０ ｋｅｙで注入し、ｐ＋ｎ接合
の形成のためにはドーズ量１０１５偽−２台のＢ＋をエ
ネルギー１０ｋｅｙで注入した（第３図）。ＣＶＤ法に
より層間絶縁膜６を２５０ ｎｍ堆積した後、注入不純
物の活性化と層間絶縁膜６の稠密化のため電気炉により
９００°Ｃ，ａｏ分間の熱処理を行った（第４図）。結
果としそ、９００”Ｃ，３０分間の熱処理の後もチタン
シリサイド層４の凝集による表面粗れが少ないチタンシ
リサイド化接合が得られた。Next, a lamp annealer that can introduce nitrogen gas is used to
Heat treatment is performed for 60 seconds at a temperature range of 00 to 650'C to silicide titanium on the silicon substrate. H2s04
When titanium nitride is selectively removed using the +-ρ2 solution, titanium silicide does not creep up (lateral growth) onto the isolation oxide film, and the titanium silicide layer 4 is formed only on the silicon. Further, in order to disilicide the titanium silicide layer 4, the temperature is set at 760 to 800° in a nitrogen atmosphere.
Lamp annealing is performed again in the temperature range of C. then n+p
To form a junction, As+ at a dose of 1015 cm-2 was implanted at an energy of 80 key, and to form a p+n junction, B+ at a dose of 1015 cm-2 was implanted at an energy of 10 key (3rd figure). After depositing the interlayer insulating film 6 to a thickness of 250 nm by the CVD method, heat treatment was performed at 900° C. for AO minutes in an electric furnace to activate the implanted impurities and densify the interlayer insulating film 6 (FIG. 4). As a result, a titanium silicided bond with less surface roughness due to agglomeration of the titanium silicide layer 4 was obtained even after heat treatment at 900''C for 30 minutes.
発明の効果
以上のように本発明は半導体装置の高集積化・高速化に
伴い、ＭＯＳＦＥＴのソース／ドレインなど浅い拡散層
上に自己都合的に、大規模集積回路製造上必要とされる
９００°Ｃ２３０分間程度の熱処理を経ても均一性の損
われないチタンシリサイド層を形成することを可能にす
るものであり、超微細な半導体装置の製造に大きく寄与
するものである。Effects of the Invention As described above, with the increasing integration and speed of semiconductor devices, the present invention conveniently provides the 900° angle required for manufacturing large-scale integrated circuits on shallow diffusion layers such as MOSFET sources/drains. C2 It is possible to form a titanium silicide layer whose uniformity is not impaired even after heat treatment for about 30 minutes, and it greatly contributes to the production of ultra-fine semiconductor devices.
第１図〜第４図は本発明の一実施例における半導体装置
の製造方法を説明するための断面図である。
１・・・・・・シリコン基板、２・・・・・・素子間分
離用酸化膜、３・・・・・・金属チタン被膜、４・・・
・・・チタンシリサイド層、５・・・・・・ｐｎ接合面
、６・・・・・・層間絶縁膜。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名−（
’Ｊ 笥 廿 わ く
翫 城
滅 憾1 to 4 are cross-sectional views for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film for isolation between elements, 3... Metal titanium coating, 4...
. . . Titanium silicide layer, 5 . . . PN junction surface, 6 . . . Interlayer insulating film. Name of agent: Patent attorney Toshio Nakao and one other person (
'J
Claims (1)
タンシリサイド膜で裏打ちされた浅い接合を形成するに
際し、前記シリコン基板にアルゴンイオンによる逆スパ
ッタリングを加え自然酸化膜の除去をするとともにシリ
コン基板の活性面を露出させた直後、金属チタン被膜を
堆積し、さらにこのチタン／シリコン界面をミキシング
するためシリコンイオン注入を行うことによって耐熱性
の高いチタンシリサイドを自己整合的に形成するように
した半導体装置の製造方法。When forming a shallow junction lined with a titanium silicide film on a silicon substrate on which an insulating film for isolation between elements has been formed, reverse sputtering with argon ions is applied to the silicon substrate to remove the native oxide film, and the silicon substrate Immediately after exposing the active surface of the semiconductor, a metallic titanium film is deposited, and silicon ions are implanted to mix the titanium/silicon interface, forming a highly heat-resistant titanium silicide in a self-aligned manner. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7465087A JPS63240017A (en) | 1987-03-27 | 1987-03-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7465087A JPS63240017A (en) | 1987-03-27 | 1987-03-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63240017A true JPS63240017A (en) | 1988-10-05 |
Family
ID=13553319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7465087A Pending JPS63240017A (en) | 1987-03-27 | 1987-03-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63240017A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143422A (en) * | 1988-11-24 | 1990-06-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04226025A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method forming titanium silicide con- ducting layer on silicon wafer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177926A (en) * | 1983-03-28 | 1984-10-08 | Nec Corp | Manufacture of semiconductor device |
| JPS60193380A (en) * | 1984-03-15 | 1985-10-01 | Nec Corp | Manufacture of semiconductor device |
| JPS6237370A (en) * | 1985-08-12 | 1987-02-18 | Mitsubishi Electric Corp | Sputtering device |
-
1987
- 1987-03-27 JP JP7465087A patent/JPS63240017A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177926A (en) * | 1983-03-28 | 1984-10-08 | Nec Corp | Manufacture of semiconductor device |
| JPS60193380A (en) * | 1984-03-15 | 1985-10-01 | Nec Corp | Manufacture of semiconductor device |
| JPS6237370A (en) * | 1985-08-12 | 1987-02-18 | Mitsubishi Electric Corp | Sputtering device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143422A (en) * | 1988-11-24 | 1990-06-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH04226025A (en) * | 1990-04-16 | 1992-08-14 | Applied Materials Inc | Method forming titanium silicide con- ducting layer on silicon wafer |
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