JPS63108749A - Gate array integrated circuit - Google Patents

Abstract

PURPOSE:To ignore a clock skew thereby to facilitate a timing design by providing one clock driver in a peripheral region, and wiring the output terminal of the driver with clock wirings. CONSTITUTION:A clock driver 4 is provided in a peripheral region 6, clock wirings 3 drawn in parallel with all transistor rows 1 are prepared for wiring regions 2, and the output terminal of the driver 4 is wired by wirings 5 to the wirings 3. Accordingly, since the simultaneous timing of the clocks in all the circuits is proved by the drivers 4, the wirings 5, and the clock wirings 3, a clock skew can be ignored.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention is directed to gate array large-scale integrated circuits (hereinafter referred to as LS).
Regarding the configuration of the gate array LS (referred to as I), the gate array LS is particularly suitable for realizing a logic circuit that operates synchronously by a clock signal.
Regarding the configuration of I.

<Prior art> In order to realize a logic circuit that operates synchronously with a clock signal using a conventional gate array LSI, a plurality of driver blocks with relatively low driving capacity prepared as functional blocks are used to generate a clock signal. A method is adopted in which signals are distributed in multiple stages, and the placement of these driver blocks and wiring for distribution are automatically performed using an automatic placement and wiring program.

<Problems to be Solved by the Invention> In the conventional gate array described above, the clock distribution system has multiple stages and is automatically placed and wired, so that the skew of the clock distribution system becomes large. As a result, it is necessary to fully consider the skinny nature of the tarock distribution system at the logic design stage, and to design with a margin in mind to absorb these skews at the time of timing design. Therefore, there is a problem that the logic design including the timing design is complicated, and the performance that can be achieved is deteriorated by the margin.

<Means for Solving the Problems> The present invention provides a gate array comprising an internal region having transistor regions arranged in an array and a wiring region provided between each transistor column, and a peripheral region thereof. The integrated circuit includes at least one clock driver circuit in the peripheral region, a clock wiring arranged in a wiring region in the internal region in parallel with the transistor array, and an output terminal of the clock driver circuit. and the above-mentioned clock wiring are connected.

According to the gate array integrated circuit according to the present invention, the synchronism of clock 9 in all circuits is guaranteed by the clock driver circuit, wiring, and clock wiring provided in advance, so that the number of gate stages in the lock distribution system is reduced compared to the conventional one. Clock skew due to differences in clock signals, clock signal wiring lengths, and loads can be almost ignored, making timing design easier at the logic design stage. Furthermore, wiring design is also facilitated because the clock signals are wired in advance.

<Example> Next, the present invention will be explained with reference to the drawings.

The accompanying drawings illustrate one embodiment of the invention. Gate array LS
I8 includes an internal region 7 having a plurality of transistor rows 1 and a wiring region 2, and a peripheral region 6. In order to realize the desired function in the gate array LSI 8, the internal region 7
This can be realized by connecting each transistor in each transistor row 1 formed in the area using the wiring area 2, and further connecting to circuits such as an input buffer circuit and an output buffer circuit provided in the peripheral area 6.

In this embodiment, a clock driver circuit 4 is provided in the peripheral area 6.
A clock wiring 3 is provided in the wiring area 2 in parallel with all the transistor rows 1, and the output terminal of the clock driver circuit 4 is connected to each clock wiring 3 by a wiring 5. is suitable for realizing a -phase synchronous circuit using a gate array LSI. Pre-provided clock driver circuit 4, wiring 5, and clock distribution! Since the iA3 guarantees the simultaneity of clock 9 in all circuits, clock skew caused by differences in the number of gate stages in the lock distribution system, clock signal wiring length, and load can be almost ignored, making it easier to use at the logic design stage. Timing design becomes easier. Furthermore, wiring design is also facilitated because the clock signals are wired in advance.

Note that in this embodiment, one clock driver circuit is provided in the peripheral area to be suitable for a one-phase synchronous circuit, and its output terminal is connected to each clock wiring. It goes without saying that a driver circuit and a plurality of clock wiring lines can be realized using the present invention.

<Effects of the Invention> As explained above, the present invention provides a gate array integrated circuit consisting of transistor regions arranged in an array and a wiring region provided between each transistor column, in which at least one clock signal is provided in the peripheral region. Has a driver circuit,
Since the wiring area in the internal area has a clock wiring drawn in parallel with the transistor array, and the output terminal of the clock driver circuit and the clock wiring are connected, the synchronization of the clock signals can be guaranteed and the logic Timing design at the design stage becomes easier.

Further, according to the present invention, since a timing margin considering clock skew is not required, a gate array integrated circuit suitable for high-speed logic circuits can be provided. Further, since the clock driver circuit is located in the peripheral area and the clock signal wiring in the internal area is parallel to the transistor array, it can be realized without affecting the conventional automatic wiring program.

[Brief explanation of the drawing]

The accompanying drawing is a block diagram showing one embodiment of the present invention. 1...Transistor row/ 2... Wiring area, 3...Clock wiring. 4...clock driver circuit, 5...Wiring, 6... Peripheral area. 7...Inner area, 8...Gate array integrated circuit.

Claims (1)

[Claims] A gate array comprising an internal region having a region of transistors arranged in an array and a wiring region provided between each transistor column consisting of a plurality of transistors, and a peripheral region provided around the internal region. In the integrated circuit, at least one clock driver circuit is provided in the peripheral area, and the wiring area has a clock wiring arranged in parallel with the transistor array, and the output terminal of the clock driver circuit and the clock wiring are connected to each other. A gate array integrated circuit characterized in that a gate array integrated circuit is connected.