JP4052339B2 - Drive circuit, active matrix substrate, and display device - Google Patents

Description

  The present invention relates to a drive circuit, an active matrix substrate, and a display device.

  In an active matrix liquid crystal display device using a thin film transistor (hereinafter referred to as TFT) as a switching element, an active matrix driving circuit is configured by a TFT, and the TFT configuring the driving circuit is defined as a TFT in a pixel portion. If it can be formed on the active matrix substrate at the same time, there is no need to mount a driver IC, which is convenient.

  However, TFTs are slower in operation speed than transistors integrated on a single crystal silicon substrate, and there is a certain limit to speeding up the drive circuit. If the drive circuit is operated at high speed, the power consumption increases accordingly. To do.

  As an example of a technique for operating a driving circuit of a liquid crystal display device at high speed, there are a technique described in Patent Document 1 and a technique described in Non-Patent Document 1.

  In the technique described in Patent Document 1, the drive circuit is configured by a plurality of shift registers, and each shift register is driven by a clock having a slightly different phase, thereby improving the substantial operating frequency of the shift register. It is.

  Non-Patent Document 1 discloses a technique for simultaneously driving a plurality of analog switches by one output of a timing control circuit and writing video signals in parallel.

  As an example of a technique for reducing the power consumption of the drive circuit, there is a technique described in Patent Document 1. In this technique, the drive circuit is divided into a plurality of blocks, and only the blocks that must operate are set in an operating state, and the other blocks are set in a non-operating state, thereby reducing power consumption.

  However, when the technique disclosed in Patent Document 1 is implemented, it is necessary to prepare a plurality of clocks having different phases, which leads to a complicated circuit configuration and an increase in the number of terminals.

  In addition, since the technique described in Non-Patent Document 1 drives a plurality of analog switches all at once, it is necessary to prepare a buffer that can load a heavy load and therefore can drive a heavy load. Also, the drive timing of each analog switch is likely to shift due to the delay of the drive signal.

  Further, the technique described in Patent Document 1 requires a control circuit for selectively operating the divided blocks, resulting in circuit complexity, and this technique increases the speed of the drive circuit. Does not contribute at all.

Furthermore, when the above-described prior art drive circuit is composed of TFTs, the circuit is complicated in any case, and it is difficult to accurately and quickly inspect the electrical characteristics of the circuit, and thus there is a problem in terms of reliability evaluation. There is.
JP 61-032093 A Japanese Patent Laid-Open No. 05-028789 JP 05-219461 A Japanese Patent Laid-Open No. 3-217891 SID Digest, pp 609-612 (1992)

  The present invention provides a novel display device, an active matrix substrate used for the display device, or a driving circuit, which has been made in consideration of the above-described problems of the prior art.

  The driving circuit according to the present invention is electrically connected to the shift register, the first output enable signal line, the second output enable signal line, the shift register, and the first output enable signal line. Electrically connected to the first NAND gate, the second NAND gate electrically connected to the shift register and the second output enable signal line, the video signal line, the video signal line, and the first NAND gate. And a second switch electrically connected to the video signal line and the second NAND gate.

  In the drive circuit, the first output enable signal line outputs a first output enable signal to the first NAND gate, and the second output enable signal line outputs a second output enable to the second NAND gate. When the second output enable signal is high level during the selection period, the first output enable signal is low level, and when the second output enable signal is low level, the first output enable signal is low level. The output enable signal is preferably at a high level.

  In the driving circuit, it is preferable that the first switch is a first analog switch.

  The drive circuit further includes a first latch circuit and a D / A converter, the first switch is included in the first latch circuit, and an output from the first latch circuit is the D / A converter is preferably input.

  The drive circuit further includes a first latch circuit, a second latch circuit, and a D / A converter, wherein the first switch is included in the first latch circuit, It is preferable that an output is input to the second latch circuit, and an output from the second latch circuit is input to the D / A converter.

  Furthermore, an active matrix substrate according to the present invention includes a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and any one of the drive circuits, and the first switch and the plurality of the plurality of scanning lines. One of the data lines is electrically connected.

  The active matrix substrate according to the present invention includes a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and the driving circuit, and the D / A converter and the plurality of data. One of the wires is electrically connected.

  In addition, the display device according to the present invention includes a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and any one of the driving circuits, and the first switch and the plurality of the plurality of scanning lines. One of the data lines is electrically connected. The display device according to the present invention includes a plurality of scanning lines, a plurality of data lines intersecting with the plurality of scanning lines, and the driving circuit, and the D / A converter and the plurality of data lines. Any of the above may be electrically connected.

  Hereinafter, the content of the present invention will be described in more detail using embodiments of the present invention.

(Embodiment 1)
(overall structure)
FIG. 1A shows a configuration of an embodiment of a liquid crystal display device according to the present invention, and FIG. 1B is a diagram showing a configuration of a pixel portion in an active matrix liquid crystal display device.

  The present embodiment is a liquid crystal display device that employs a method of driving a data line using an analog switch (switch circuit).

  In this embodiment, a TFT is used as a transistor constituting the data line driving circuit. The TFT is formed on the substrate simultaneously with the switching TFT in the pixel portion. The manufacturing process will be described later.

  One pixel in the pixel portion (active matrix) 300 includes a switching TFT 350 and a liquid crystal element 370 as shown in FIG. 1B. The gate of the TFT 350 is connected to the scanning line L (k), and the source (drain) is connected to the data line D (k).

  The scanning line L (k) is driven by the scanning line driving circuit 100 shown in FIG. 1A, and the data line D (k) is driven by the data line driving circuit 200 shown in FIG. 1A.

  The data line driving circuit 200 is connected to a shift register 220 having at least the number of stages corresponding to the number of data lines, a gate circuit 240, and N (four in this embodiment) video signal lines (S1 to S4). A plurality of analog switches 261.

  The fact that N video signal lines (S1 to S4) are prepared means that the video signals are multiplexed and the multiplicity thereof is “N”.

  The plurality of analog switches are grouped every arbitrary M (in this embodiment, every four), and the total number of the groups is equal to the total number of video signal lines (ie, “N”). That is, in this embodiment, the number of groups of analog switches is “4”, and each analog switch belonging to one group is commonly connected to one video signal line.

  In FIG. 1A, “V1”, “V2”, “V3”, “V4” indicate multiplexed video signals, “SP” indicates a start pulse input to the shift register 220, “CL1”, “V1” “nCL1” indicates an operation clock. “CL1” and “nCL1” are pulses whose phases are shifted by 180 degrees. In the following description, for other pulse signals, a clock whose phase is shifted by 180 degrees is represented by “n” at the beginning. A positive pulse corresponds to a digital value “1”, and a negative pulse corresponds to a digital value “0”.

  The meaning of the multiplexing of the video signal is shown in FIG. 4B. As shown in FIG. 4A, when the first to sixteenth video signals are taken as an example, each signal is usually arranged in order in time series.

  On the other hand, when the video signal is multiplexed with the multiplicity “4” as in the present embodiment, as shown in FIG. 4B, the video signals V1 to V4 are “first” and “fifth” at time t1, respectively. , “9th” and “13th” signals appear simultaneously. Similarly, at time t2, “second”, “sixth”, “tenth”, “14th” signals appear simultaneously, and at time t3, “third”, “seventh”, “ The eleventh and fifteenth signals appear simultaneously, and the fourth, eighth, twelfth, and sixteenth signals appear at time t4.

  Multiplexing of video signals is possible, for example, by delaying an analog video signal little by little and creating a plurality of video signals having slightly different phases as shown in FIG. Such a delay of the video signal can be realized by using, for example, a delay circuit 1200 as shown in FIG. The delay circuit 1200 is formed by connecting four delay circuits 1202 to 1207 having the same delay amount in series, and supplies the output of each delay circuit to the data line driving circuit 200. In FIG. 5, reference numeral 1000 is an analog video signal generator, and reference numeral 1100 is a timing controller.

  In this embodiment, video signals are multiplexed in this way, while a single shift register is used to simultaneously generate a number of pulses corresponding to the degree of multiplicity, and a plurality of analog switches are driven simultaneously to generate video. By supplying signals to a plurality of data lines at the same time, the data line drive speed can be increased.

  Note that the liquid crystal display device is actually configured by bonding an active matrix substrate 3100 and a counter substrate 3000, as shown in FIG. Liquid crystal is sealed between the substrates.

(Specific configuration of data line driving circuit)
The present embodiment is characterized in the operation of the data line driving circuit 200, and will be specifically described below.

  As shown in FIG. 2, in the present embodiment, in the shift register 220, a plurality of positive polarity pulses (one pulse corresponds to data “1”) are simultaneously shifted at a predetermined interval, and this is supported. Then, a plurality of pulses that run in parallel at intervals are output from each stage of the shift register. The number of pulses running in parallel is equal to the multiplicity “N” of the video signal. That is, in the present embodiment, the number is “4”.

  Those pulses are used to determine the operation timing of the analog switch 261. Specifically, these pulses are input to the gate circuit 240, and a plurality of pulses that run in parallel at intervals are output from the output terminals (OUT1 to OUT (N × M)) of the gate circuit 240. The

  In this embodiment, those pulses output from the gate circuit 240 are used to determine the timing of sampling of the video signal by the analog switch.

  The gate circuit 240 is used for waveform shaping. That is, there is a difference in voltage-current characteristics between the p-type TFT and the n-type TFT, as shown in FIG. 23A. Therefore, when these TFTs are used as output stage transistors, a buffer as shown in FIG. 23B is configured. As shown in FIG. 23C, the output waveform becomes dull with respect to the pulse input, and a signal delay occurs. In order to suppress such a delay, it is desirable to provide the gate circuit 240. However, this is not always necessary, and the analog switch 261 may be directly driven by the output signal of the shift register 220.

  A more specific circuit configuration of the data line driving circuit 200 is shown in FIG.

  As clearly shown in FIG. 3, the analog switch 261 is configured by a MOS transistor 410. Reference numeral 412 denotes a capacity of the data line itself (hereinafter referred to as data line capacity).

  One stage (reference number 500) constituting the shift register 220 includes an inverter 504 and clocked inverters 502 and 506.

  In addition, the gate circuit 240 includes 2-input NAND gates 241 to 246 that receive outputs of two adjacent stages of the shift register.

(Explanation of circuit operation)
Next, the operation of the circuit shown in FIG. 3 will be specifically described with reference to FIGS. 9 and 10. 9 and 10 show examples of N = 4 and M = 10. FIG. 9 shows an initial stage operation among the operations until four pulses running in parallel from the shift register 220 are steadily output (the state is shown in FIG. 10).

9, “a” to “g” indicate signal waveforms at the output terminals of the respective stages of the shift register 220 shown in FIG. 3, and “OUT1” to “OUT6” are NAND gates also shown in FIG. The waveforms of output signals 241 to 246 are shown. “GP” is a selection pulse of one scanning line, “H ₁ ” indicates the first selection period in the non-stationary state, and “H ₂ ” indicates the second selection period in the non-stationary state. “H ₃ ” indicates the third selection period in the non-stationary state. As described above, “CL1” and “nCL1” are operation clocks, and “SP” is a start pulse. The same applies to FIG.

  As shown in FIG. 9, when one start pulse (SP) is sequentially input to the shift register 220 in one selection period (1H), one pulse is output from each stage of the shift register 220 correspondingly. Are output, and the pulses are sequentially shifted. In response to this, one pulse is sequentially output from each of the NAND gates 241 to 246.

Such an operation is repeated, and as shown in FIG. 10, the fourth selection period is the first selection period “H _1th ” in the steady state, and at the start time (time t 1), four pulses are first _displayed. Are simultaneously output from the gate circuit 240 (OUT1, OUT11, OUT21, OUT31). Thereafter, the pulses run in parallel in the same direction while maintaining a mutual interval, and a state in which four pulses are output simultaneously is steadily realized.

  With the four pulses output at the same time, the MOS transistors 410 constituting the analog switches 261 in FIG. 3 are simultaneously turned on, and the multiplexed video signals are sampled at the same time. Video signals are simultaneously supplied to the data lines.

  That is, when a pulse is input, the MOS transistor 410 is turned on, the data line (D (n)) and the video signal lines (S1 to S4) are electrically connected, and the analog video signal is written to the data line capacitor 412. It is. When the MOS transistor 410 is turned off, the written signal is held in the data line capacitor 412. That is, the data line capacitance 412 serves as a holding capacitor. Since the data line driver is composed of only analog switches, the circuit configuration is simple, the degree of integration can be increased, and the video signal can also be sampled accurately. In the case of a relatively small liquid crystal panel, the data line can be sufficiently driven by a driver having only an analog switch as in this embodiment.

  Thus, in this embodiment, first, a plurality of pulses are generated simultaneously using a single shift register. Therefore, the frequency of the output signal of the shift register can be increased without changing the frequency of the operation clock of the shift register. When the number of simultaneously generated pulses is “N (N is a natural number of 2 or more)”, the frequency of the output signal of the shift register is N times.

  Then, by using each output signal of the shift register to determine the sampling timing of the video signal by the analog switch, high-speed data line driving is realized. Therefore, even if the driving circuit of the liquid crystal display matrix is constituted by TFTs, high-speed data lines can be driven without increasing power consumption.

  As an analog switch, not only a single MOS transistor but also a CMOS switch as shown in FIG. 25A can be used. The CMOS switch is composed of MOS transistors 414 and 416 and an inverter 418.

  Further, an analog driver as shown in FIG. 25B can be used as the data line driver. The analog driver includes a sample / hold circuit including a MOS transistor 440 and a holding capacitor 420 and a buffer circuit (voltage follower) 400.

  Further, the present embodiment has excellent unique effects as described below. Hereinafter, the effect will be described in comparison with the comparative example.

(Contrast with comparative example)
FIG. 11A is a diagram showing a configuration of a data line driving circuit of a comparative example, and FIG.

  In the comparative example of FIG. 11A, a plurality of shift registers (SR) and gate circuits are provided (222 to 226, 242 to 246), and a start pulse (SP) is individually supplied to each of the shift registers (SR). Yes. It is necessary to input the start pulse to the shift register via the dedicated wiring S10.

  In this case, the start pulse input wiring S10 intersects with the wiring S20 for inputting the operation clock (CL1, nCL1) to each of the shift registers 222, 224, and 226. As a result, as shown in FIG. Noise is superimposed on the pulse.

  Further, the length of the input line S10 for the start pulse is at least about 10 μm, which is a major obstacle to miniaturization.

  Furthermore, the start pulse is delayed by the resistance of the wiring, and there is a possibility that the input timing to each shift register may be different.

  On the other hand, in the data line driving circuit of this embodiment, as shown in FIG. 12A, a start pulse (SP) may be input at a desired timing from the left end of one shift register 220. Dedicated wiring is not required.

  Therefore, in this embodiment, noise is not superimposed on the start pulse as shown in FIG. 11B, and the layout area can be reduced.

  In addition, since a plurality of pulses are generated using a single shift register, the start pulse is not delayed.

  Thus, according to the present invention, both circuit miniaturization and reduction in the frequency of the operation clock of the shift register can be achieved. Therefore, for example, even when a TFT formed using a low-temperature process is used as a TFT constituting the data line driving circuit, high-speed and accurate operation is ensured.

  Therefore, if this embodiment is used, the performance of the liquid crystal display device in which the drive circuit is composed of TFTs can be improved.

(TFT manufacturing process)
22A to 22E show an example of a manufacturing process (low-temperature manufacturing process) in the case where the TFT of the driver part and the TFT of the active matrix part (pixel part) are formed on the substrate at the same time. The TFT manufactured by this manufacturing process is a TFT having a LDD (Lightly Doped Drain) structure using polysilicon.

  First, an insulating film 4100 is formed on a glass substrate 4000, polysilicon islands (4200a, 4200b, 4200c) are formed on the insulating film 4100, and then a gate oxide film 4300 is formed on the entire surface (FIG. 22A).

  Next, after forming the gate electrodes 4400a, 4400b, and 4400c, mask materials 4500a and 4500b are formed, and then boron is ion-implanted at a high concentration to form p-type source / drain regions 4702 (FIG. 22b). ).

  Next, the mask materials 4500a and 4500b are removed, and phosphorus is ion-implanted to form n-type source / drain regions 4700 and 4900 (FIG. 22C).

  Subsequently, after forming mask materials 4800a and 4800b, phosphorus is ion-implanted (FIG. 22D).

  Subsequently, an interlayer insulating film 5000, metal electrodes 5001, 5002, 5004, 5006, 5008, and a final protective film 6000 are formed to complete the device.

(Embodiment 2)
The present invention can be applied not only to a data line driving circuit using an analog driver but also to a data line driving circuit using a digital driver.

  FIG. 8 shows a configuration example of a data line driving circuit of a line sequential driving method using a digital driver.

  This circuit is characterized by a first latch 1500 that captures and temporarily stores digital video signals (V1a to V1d), and data of each bit of the first latch 1500 is collectively captured and temporarily stored. And a D / A converter 1600 that simultaneously converts the digital data of each bit of the second latch 1510 into an analog signal and drives all the data lines simultaneously. is there.

  Even in a circuit using such a digital driver, the technique shown in the above-described first embodiment can be applied as a method of taking digital video signals (V1a to V1d) into the first latch 1500. That is, by multiplexing digital video signals (V1a to V1d), simultaneously generating a plurality of pulses from one shift register 220, and latching a plurality of data of the digital video signal in parallel using these pulses. The digital video signal latch can be speeded up without increasing the frequency of the operation clock of the shift register.

  Multiplexing of digital video signals can be realized, for example, by a data rearrangement circuit 1270 shown in FIG. In FIG. 7, reference numeral 1000 indicates an analog video signal generator, reference numeral 1250 indicates an A / D conversion circuit, reference numeral 1260 indicates a γ correction ROM, and reference numeral 1110 indicates a timing controller.

  Note that the present invention is not limited to the line-sequential drive type digital driver, and can also be applied to a dot-sequential drive type digital driver.

(Embodiment 3)
The features of the third embodiment of the present invention are shown in FIGS. 19A and 19B. In the first embodiment, the gate circuit 240 is composed of a NAND gate (FIG. 3), but in this embodiment, the gate circuit 240 is composed of an exclusive OR gate 251. The exclusive OR gate 251 receives the outputs (a, b...) Of two adjacent stages of the shift register as inputs, and uses pulses (X, Y, Z,...) Used to determine the sampling timing of the video signal.・ ・) Is output.

  The advantage of using the exclusive OR gate 251 is that power consumption can be reduced when one period of the start pulse (SP) is two selection periods (twice the selection period), and the trailing edge of the output pulse is steep. Thus, the pulse width can be prevented from widening.

  That is, as shown in FIG. 3, assuming that one cycle of the start pulse (SP) is two selection periods (twice the selection period), pulses are output in parallel by the same circuit operation as shown in FIG. At the same time, the number of level changes of the outputs (a, b...) Of each stage of the shift register per selection period is halved compared to the case where the operation as shown in FIG. 9 is performed.

  That is, the signal level change within one selection period (1H) at the point “b” in FIG. 19A is once as shown in FIG. 19B. That is, there is only one positive edge R3 in one selection period (1H).

  On the other hand, in the circuit operation shown in FIG. 9, the signal level at the point “b” changes twice within one selection period (1H). That is, there are two positive edges R1 and negative edges R2 in one selection period (1H). Therefore, compared with the case of FIG. 9, in the case of FIG. 19, the number of signal level transitions is halved, and accordingly, the power consumption is reduced to about half.

  24B, in the case of a two-input NAND gate (shown in FIG. 24A), the pulse width (T1) of the output pulse is determined by the positive edge of one input and the negative edge of the other input. On the other hand, in the case of the 2-input exclusive OR gate (FIG. 24C), as shown in FIG. 24D, the pulse width (T2) of the output pulse is determined by the positive edges of the two inputs. For this reason, it is possible to prevent the trailing edge of the output pulse from becoming steep and the pulse width from widening.

(Embodiment 4)
FIG. 13A shows the main configuration of the fourth embodiment of the present invention.

  A feature of this embodiment is that the gate circuit 240 in FIG. 1 is a NAND gate (241, 242, 243, 244...) That receives the output of each stage of the shift register and the output enable signal (E, nE). It is configured.

  Since the control by the output enable signal (E, nE) is enabled, the output level of the shift register and the output level of the gate circuit can be controlled independently. By utilizing this feature, pulse generation (negative edge generation) from the NAND gates (241, 242, 243, 244...) Can be temporarily interrupted during circuit operation. As a result, the generation of pulses can be resumed.

  For example, in FIG. 13B, from time t4 to time t6 (period TS1), the generation of pulses from the NAND gates (241, 242, 243, 244...) Is stopped, and the generation of pulses is resumed at time t6. Think about the case.

  In such an operation, the operation clocks CL1 and nCL1 are stopped in the period TS1, while the output enable signal (E) is fixed at a low level from time t4 to time t5, and at the time t5, the same cycle as that of the operation clock. This is realized by resuming changes in For the output enable signal (nE), the change in the same cycle as the operation clock may be resumed from time t6.

  A technique for stopping the generation of such a pulse can be used, for example, to prohibit sampling of a video signal in a horizontal blanking period (BL).

  FIG. 14 shows an operation in an actual circuit when the generation of pulses from the gate circuit is stopped during the horizontal blanking period (time t12 to t13). In FIG. 14, for example, “157” indicates “output of the 157th stage” of one shift register, and “OUT159” indicates “output of the 159th NAND gate”.

  As clearly shown in FIG. 14, in order to stop the generation of pulses from the gate circuit during the horizontal blanking period (time t12 to t13), the operation clock (CL1, nCL1) and the enable signal at time t1 to t14. (N, nE) may be stopped.

(Embodiment 5)
The liquid crystal display device shown in FIG. 1 is also suitable for inspection of electrical characteristics such as data lines. That is, as shown in the upper side of FIG. 15, by providing the test signal input circuit 2000, the frequency characteristics of the data lines and analog switches, the disconnection of the data lines, and the like can be detected accurately and quickly.

  In FIG. 15, the test signal input circuit 200 is connected to one end of the data line, and the video signal input line S <b> 1 is connected to the other end of the data line via the analog switch 261. In FIG. 15, “TG” indicates a test enable signal, and “TC” indicates a power supply voltage.

  The inspection is performed as follows.

  First, the test enable signal “TG” is activated, and the power supply voltage (inspection voltage) is supplied to each data line at once.

  In such a voltage application state, one pulse is sequentially output from one shift register. Then, one pulse is sequentially output from the gate circuit 240. The analog switch is sequentially turned on by the pulse, whereby the voltage supplied from one end of the data line can be received via the analog switch 261 and the video signal input line S1, and thereby the data line and the analog switch can be received. Inspection of electrical characteristics can be performed.

  As described above, in this embodiment, it is necessary to sequentially generate pulses one by one from one shift register. That is, the data lines are arranged as shown in FIG. 16A. In the above-described embodiment, a method of simultaneously driving a plurality of data lines as shown in FIG. 16B is adopted. As shown in 16C, it is necessary to switch to a method of sequentially driving one by one.

Such switching can be easily performed by changing the input method of the start pulse as shown in FIG. That is, as shown in FIG. 17, if one start pulse (SP) is input at the beginning of the first selection period (H _1st ) and the pulse is shifted over the entire number of stages, one pulse is sequentially applied. If one start pulse (SP) is input for each selection period, a plurality of pulses can be generated simultaneously as shown in FIG.

  By sequentially generating pulses one by one from one shift register, the electrical characteristics of the data lines can be examined one by one, and the inspection becomes easy.

  When the configuration shown in FIG. 18A is used, as shown in FIG. 18B, if the operation clocks CL1 and nCL1 of the shift register are stopped in a predetermined period TS3, only the output (OUT1) of the NAND gate is used during that period. Becomes high level. Therefore, only the corresponding analog switch is turned on, and only the first data line can be inspected carefully during the predetermined period TS3.

  In FIG. 20, a line-sequential digital driver 214 (same configuration as that in FIG. 8) may be provided instead of the dedicated test signal input circuit 2000. In this case, the digital driver 214 also functions as an inspection signal input circuit in addition to the function of driving the original data line.

  In the configuration of FIG. 20, both data line driving based on an analog video signal and data line driving based on a digital video signal are possible.

  If the liquid crystal display device according to the present invention described above is used as a display device in a device such as a personal computer, the value of the product is improved.

FIG. 1A is a diagram illustrating an overall configuration of an embodiment of a liquid crystal display device according to the present invention, and FIG. 1B is a diagram illustrating a configuration of a pixel portion. It is a figure for demonstrating the characteristic of embodiment shown by FIG. FIG. 3 is a circuit diagram showing the circuit configuration shown in FIG. 2 more specifically. FIG. 4A is a diagram showing the data arrangement of the original video, and FIG. 4B is a diagram showing an example of the data arrangement when the data of the original video is arranged in time series by the method used in the present invention. It is a figure which shows the example of a circuit structure for processing an analog video signal into the multiplexed signal as shown by FIG. 4B. FIG. 6 is a diagram for explaining main operations of the circuit of FIG. 5. It is a figure which shows the example of a circuit structure for processing a digital video signal into the multiplexed signal as shown by FIG. 4B. It is a figure which shows the structural example of the liquid crystal matrix drive circuit of a digital line sequential system. 4 is a timing chart showing operation timings of the circuits shown in FIGS. 1A, 2 and 3. FIG. FIG. 10 is a timing chart showing the output timing of the output signal of the analog switch 261 in the circuits shown in FIGS. 1A, 2 and 3. FIG. 11A is a diagram showing a circuit configuration of a comparative example, and FIG. 11B is a signal waveform diagram showing a problem of the circuit of FIG. 11A. FIG. 12A is a diagram showing an essential part of the liquid crystal display device according to the present invention shown in FIGS. 1 to 3, and FIG. 12B is a signal waveform diagram showing advantages of the circuit of FIG. 12A. FIG. 13A is a diagram showing a main configuration of another embodiment of the liquid crystal display device according to the present invention, and FIG. 13B is a timing chart for explaining an operation example of the circuit of FIG. 13A. 13B is a timing chart showing another operation example of the circuit shown in FIG. 13A. It is a figure which shows the whole structure of other embodiment of the liquid crystal display device which concerns on this invention. 16A is a diagram showing an arrangement of data lines in the circuit of FIG. 15, FIG. 16B is a diagram showing a normal operation of the drive circuit according to the present invention, and FIG. 16C is a defect inspection of the drive circuit of FIG. 16B. FIG. FIG. 16D is a timing chart for more specifically explaining the operation at the time of defect inspection of the drive circuit according to the present invention shown in FIG. 16C. FIG. 18A is a diagram illustrating a configuration of a main part of the drive circuit according to the present invention, and FIG. 18B is a diagram illustrating an example of an operation at the time of defect inspection of the circuit of FIG. FIG. 19A is a diagram showing a main configuration of a drive circuit according to the present invention, and FIG. 19B is a timing chart showing a normal operation example of the drive circuit of FIG. 19A. It is a figure which shows the structure of other embodiment of the liquid crystal display device which concerns on this invention. It is a perspective view which shows the structure of a liquid crystal display device. FIG. 22A to FIG. 22E are cross-sectional views of devices in respective steps, showing an example of a manufacturing process for simultaneously forming TFTs constituting a driver portion and TFTs constituting an active matrix. 23A is a diagram showing voltage-current characteristics of a p-channel TFT and an n-channel TFT, FIG. 23B is a circuit diagram of a buffer circuit using the p-channel TFT and the n-channel TFT, and FIG. 23C is a diagram of FIG. It is a figure which shows the input waveform and output waveform of this circuit. 24A shows a NAND gate using a p-channel TFT and an n-channel TFT, FIG. 24B shows an input waveform and an output waveform of the circuit of FIG. 24A, and FIG. 24C shows a p-channel TFT and an n-channel TFT. FIG. 24D is a diagram showing the input OR and output waveforms of the circuit of FIG. 24C. FIG. 25A is a diagram illustrating an example of a configuration of an analog switch, and FIG. 25B is a diagram illustrating a configuration of an analog driver.

Explanation of symbols

100 scanning line driving circuit, 200 data line driving circuit, 214 digital driver, 220 shift register, 222-226, 242-246 gate circuit, 240 gate circuit, 251 exclusive OR gate, 261 analog switch, 300 pixel part (active Matrix), 350 TFT, 370 liquid crystal element, 410, 414, 416, 440 MOS transistor, 412 data line capacitance, 418, 504 inverter, 420 holding capacitor, 400 buffer circuit (voltage follower), 502, 506 clocked inverter, 1000 Analog video signal generator, 1100, 1110 timing controller, 1250 A / D conversion circuit, 1260 γ correction ROM, 1270 Circuit, 1500 first latch, 1510 second latch, 1600 D / A converter, 2000 inspection signal input circuit, 3000 counter substrate, 3100 active matrix substrate, 4000 glass substrate, 4100 insulating film, 4200a, 4200b, 4200c polysilicon island, 4300 gate oxide film, 4400a, 4400b, 4400c gate electrode, 4500a, 4500b mask material, 4702 p-type source / drain region, 4700, 4900 n-type source / drain region, 4800a, 4800b mask material, 5000 interlayer insulation film, 5001,5002,5004,5006,5008 metal electrode, 6000 final protective film, V1-V4 video signal, SP start pulse, CL1, nCL1 operation clock, t1, t2, t3, t4 time, GP scanning line selection pulse, D (n) data line, S1-S4 video signal line, SR shift register, S10 wiring, V1a-V1d digital video signal, E, nE output enable signal, BL horizontal blanking period, TG test enable signal, TC power supply voltage

Claims (10)

A first clock signal and a second clock signal that is an inverted signal of the first clock signal are input, and a start pulse is sequentially transferred according to the frequency of the first and second clock signals, A shift register that outputs an output signal ;
A first output enable signal line;
A second output enable signal line different from the first output enable signal line;
A first NAND gate;
A second NAND gate,
A first high level signal output from the first output terminal of the shift register by the first NAND gate; and a first output enable signal transmitted through the first output enable signal line. Input and set to output a first low level signal,
The second NAND gate receives a second high level signal output from a second output terminal of the shift register and a second output enable signal transmitted from the second output enable signal line; And set to output a second low level signal,
The first low level signal is set to be output in a period that does not overlap with a period in which the second low level signal is output,
In the horizontal blanking period, both the first output enable signal and the second output enable signal are set to be at a low level ,
In a period in which the plurality of output signals are output, the first clock signal is at a high level in the first period,
In a second period different from the first period, the first clock signal is fixed at a high level,
The second period includes a horizontal blanking period;
2. The driving circuit according to claim 1, wherein the second period is longer than the first period . A first clock signal and a second clock signal that is an inverted signal of the first clock signal are input, and a start pulse is sequentially transferred according to the frequency of the first and second clock signals, A shift register that outputs an output signal ;
A first output enable signal line;
A second output enable signal line different from the first output enable signal line;
A first NAND gate;
A second NAND gate,
The first NAND gate receives a first high-level signal output from the first output terminal of the shift register and a first output enable signal transmitted from the first output enable signal line; And set to output a first low level signal,
The second NAND gate receives a second high level signal output from a second output terminal of the shift register and a second output enable signal transmitted from the second output enable signal line; And set to output a second low level signal,
In a period in which the plurality of output signals are output, the first clock signal is at a high level in the first period,
In a second period different from the first period, the first clock signal is fixed at a high level,
2. The driving circuit according to claim 1, wherein the second period is longer than the first period . The drive circuit according to claim 1 or 2 ,
A drive circuit, wherein the period in which the first output enable signal is at a high level and the period in which the second output enable signal is at a high level do not overlap. The drive circuit according to any one of claims 1 to 3 , further comprising:
Video signal lines,
A first analog switch through which a video signal is transmitted from the video signal line;
A second analog switch through which a video signal is transmitted from the video signal line,
The first analog switch is controlled by the first low level signal output from the first NAND gate, and the second analog switch is output from the second NAND gate. A drive circuit characterized by being set to be controlled by The drive circuit according to any one of claims 1 to 3 , further comprising:
A video signal line for transmitting digital video signals;
A latch circuit for transmitting the digital video signal from the video signal line;
A D / A converter that converts a digital signal output from the latch circuit into an analog signal;
A first switch included in the latch circuit is controlled by the first low level signal output from the first NAND gate, and a second switch included in the latch circuit is output from the second NAND gate. The driving circuit is set to be controlled by the second low level signal. The drive circuit according to any one of claims 1 to 3 , further comprising:
A video signal line for transmitting digital video signals;
A first latch circuit for transmitting the digital video signal from the video signal line;
A second latch circuit for inputting an output from the first latch circuit;
A D / A converter that converts a digital signal output from the second latch circuit into an analog signal;
The first switch included in the first latch circuit is controlled by the first low level signal output from the first NAND gate, and the second switch included in the first latch circuit is the first switch. A drive circuit, wherein the drive circuit is set to be controlled by the second low level signal output from the second NAND gate. A plurality of scan lines;
A plurality of data lines intersecting the plurality of scanning lines;
A drive circuit according to any one of claims 1 to 4 ,
The active matrix substrate, wherein the first analog switch is set to output a signal to any of the plurality of data lines. A plurality of scan lines;
A plurality of data lines intersecting the plurality of scanning lines;
A drive circuit according to any one of claims 1 to 4 ,
The display device, wherein the first analog switch is set to output a signal to any of the plurality of data lines. A plurality of scan lines;
A plurality of data lines intersecting the plurality of scanning lines;
A drive circuit according to claim 5 or 6 ,
An active matrix substrate, wherein the D / A converter is set to output a signal to any of the plurality of data lines. A plurality of scan lines;
A plurality of data lines intersecting the plurality of scanning lines;
A drive circuit according to claim 5 or 6 ,
The display device, wherein the D / A converter is set to output a signal to any of the plurality of data lines.

Images