JP3340774B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit such as an LSI having a plurality of flip-flops, and more particularly to a semiconductor integrated circuit in which the skew of a clock signal for synchronizing each flip-flop is improved.

[0002]

2. Description of the Related Art In recent years, high integration, large scale, and high speed of semiconductor integrated circuits have been advanced, and accordingly, the necessity of improving a pattern layout and preventing a circuit malfunction has been increased. Many flip-flops provided in such an integrated circuit operate in synchronization with one clock signal, and a method of supplying a clock to this flip-flop is particularly preferable from the viewpoint of pattern layout and malfunction prevention. It is important.

In consideration of these points, as a conventional clock supply method, a method of forming a so-called clock tree by dividing and arranging clock drivers such as buffers and inverters at a plurality of locations on a substrate is often adopted. .
However, simply dividing the clock driver into a plurality of parts may cause clock skew (delay between clock signals) due to a difference in the load condition of each clock driver, and may cause a malfunction of the circuit . In order to solve this problem, for example, Japanese Patent Application Laid-Open No. 61-82525
A technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-163,878 has been proposed.

FIG. 4 is a diagram showing an outline of a clock supply system for a semiconductor integrated circuit disclosed in the above publication. In FIG. 1, an output from a clock generator 100 is supplied to clock drivers 104, 106, and 108 which are divided and arranged via a clock driver 102, and the clock drivers 104, 106, and 108 cause the clock signal lines 104a, 106a and 108a.

The clock signal lines 104a, 106a, 10
A plurality of flip-flops are connected to 8a.
For example, the flip-flops 400, 402, 404,...
6a includes flip-flops 600, 602, 604,.
Are connected respectively. And the clock signal line 1
04a, 106a, and 108a are wired to each other by a signal line 700.

As described above, the individual clock driver 10
Clock signal line 104 driven by 4, 106, 108
a, 106a, and 108a are wired to each other by a signal line 700, so that a plurality of clock drivers 10
It is assumed that the load conditions of the clock signals 4, 106, 108 become equal, and the clock skew of the clock signal obtained from each of the clock drivers 104, 106, 108 disappears.

[0007]

However, according to the technique disclosed in the above publication, although the capacitance between the flip-flops becomes the same due to the above-described wired connection, the wiring length of each clock signal line and the wired signal line is reduced. If the wiring length becomes longer and the wiring length varies, the resistance value of the signal line itself becomes different, which causes a problem that skew occurs.

Furthermore, the performance such as skew varies depending on the location where the wiring is made (distance from the clock driver, etc.). Therefore, it is necessary to sufficiently consider the pattern layout at the time of designing, and there is a problem that the design becomes complicated. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit capable of improving clock skew and preventing circuit malfunction, and simplifying a pattern layout process at the time of design. To provide.

[0010]

In order to achieve the above object, the present invention comprises a first driving means for driving a clock signal, and a high level threshold connected to an output of the first driving means. And a plurality of flip-flops having a dedicated wire terminal connected to the output side of the first driving means and operating in synchronization with the output of the second driving means. a semiconductor integrated circuit comprising the flip-flops, each of the wired
It is intended to provide a semiconductor integrated circuit characterized by being wired-connected via a dedicated terminal . Where
The wired dedicated terminal that realizes the yard connection function,
Made from the beginning inside the flip-flop at the manufacturing stage
Preferably, it is embedded.

[0011]

According to the semiconductor integrated circuit of the present invention, with the above configuration, each flip-flop is connected to a dedicated wire wired by the drive capability of the first drive means.
As the potential of the terminal (external pin) rises,
It does not operate until the high threshold level of the second drive means is reached, but only when it reaches that threshold level. Thereby, clock skew can be sufficiently absorbed.

Further, since the wired function is built into each flip-flop from the beginning by providing a wired dedicated terminal for wiring connected to the first driving means inside the flip-flop, wiring is thereafter performed. Since a wired signal line can be automatically wired at the time of processing, the trouble of pattern layout at the time of design is greatly reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor integrated circuit according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings. FIG. 1 is a schematic circuit diagram showing one embodiment of the semiconductor integrated circuit of the present invention. As shown in FIG. 1, the semiconductor integrated circuit has a clock driver 4 for driving an output from a clock generator 2, and its output side is divided and commonly connected to respective input sides of clock drivers 8, 10, and 12. Have been.
Further, the output sides of the clock drivers 8, 10, 12 are connected to clock terminals of a plurality of flip-flops via clock signal lines 8a, 10a, 12a, respectively. For example, each clock terminal of flip-flops 20, 22, 24... Is connected to the clock signal line 8a, and flip-flops 40, 42, 4 are connected to the clock signal line 10a.
4 are connected to each other.

Each of the flip-flops 20, 22, 24, ... and the flip-flops 40, 42, 44, ... is provided with a wired dedicated terminal CW, which will be described later, and the wired dedicated terminal CW is wired via a signal line 50. Have been.

FIG. 2 is a circuit diagram showing a clock supply unit of the flip-flop in FIG. 1, and shows the F / F 20 as a representative example. These flip-flops 20, 2
2, 24 ... and flip-flops 40, 42, 44 ...
FIG. 2 shows a clock terminal CKN (inverting input) for taking in clock signals sent from the clock signal lines 8a and 10a, respectively, as shown as a representative example of the F / F 20 in FIG. Data terminal D for taking in data sent from components that do not
And an output terminal Q for outputting output data, and a wired dedicated terminal CW connected to the signal line 50. Here, the wired dedicated terminal CW is formed in the flip-flops 20, 22, 24,... And the flip-flops 40, 42, 44,.
Thereafter, the signal lines 50 are arranged.

Also, flip-flops 20, 22, 24
And the clock supply unit in the flip-flops 40, 42, 44,... Have an inverter 61 (first driving means) connected to the clock terminal CKN. The output side of the inverter 61 is connected to the wired dedicated terminal CW, and is also connected to the inverters 62 and 63 sequentially. Here, the inverter 62 (second driving means) has an inversion threshold value set to a value higher than usual. Then, a clock CK and its inverted clock CK bar are output from the respective output sides of the inverters 62 and 63, and supplied to the gate circuits in the flip-flops 20, 22, 24... And the flip-flops 40, 42, 44. , The respective flip-flops 20, 22,
24 and the flip-flops 40, 42, 44,.

The semiconductor integrated circuit of the present invention is basically constructed as described above. The clock supply operation of the present embodiment will be described below. In FIG. 1, an output from a clock generator 2 is divided after being driven by a clock driver 4 and further driven by clock drivers 8, 10, 12 to generate a plurality of flip-flops via signal lines 8a, 10a, 12a. Is supplied to the clock terminal CKN. For example, the output of the clock driver 8 is supplied to each clock terminal CKN of the flip-flops 20, 22, 24,... Via the signal line 8a, and the clock driver 10 outputs the flip-flops 40, 42, 44 via the signal line 10a. Are supplied to each clock terminal CKN.

FIGS. 3A and 3B are signal waveform diagrams for explaining the clock supply operation of this embodiment. FIG. 3A shows the flip-flop 20 and the flip-flop 40.
7B is an enlarged view of the signal waveform of the wired dedicated terminal CW20. FIG. At this time, in the present embodiment, for simplicity of description, for example, the flip-flop 20 and the flip-flop 40 are taken up, and the clock signal supplied to the clock terminal CKN of the flip-flop 40 is applied to the clock terminal CKN of the flip-flop 20. A case where the clock signal arrives later than the supplied clock signal will be described as an example. In this case, the clock terminals of the flip-flops 20 and 40 are connected to C
KN20 and CKN40, the dedicated terminals for wired are respectively CW20 and CW40, and the clocks and inverted clocks are CK20 and CK4, respectively.
0, CK bar 20 and CK bar 40.

The clock terminal CK of the flip-flop 20
At time T1 when the signal level of N20 falls from the high level to the low level, first, the inverter 61
Starts driving, and the level of the wired dedicated terminal CW20 starts rising. However, the rising of the level of the wired dedicated terminal CW20 becomes gentle. This is because even if the inverter 61 of the flip-flop 20 is turned on, another flip-flop, such as the flip-flop 40, to which the clock signal arrives with a delay, for example,
This is because the inverter 61 has not been turned on yet, and the charging of the signal line 50 is delayed accordingly.

Thereafter, the delayed clock signal arrives at each clock terminal CKN of the flip-flop (time T2 shown in FIG. 3 in the example of the flip-flop 40), for example, like the flip-flop 40, and all the inverters 61 When it is turned on (time T3), the driving capacity increases,
The potential of the wired dedicated terminal CW20 of the flip-flop 20 increases rapidly, and its waveform has a steep rise. As shown in FIG. 3A, the level of the wired dedicated terminal CW40 that rises with a delay also rises rapidly with the increased driving capability.

In the period from time T3 to time T3 ', since each wired dedicated terminal CW is wired by the signal line 50, the rise of the waveform is almost the same. That is, at this point, the clock skew is almost absorbed. And
At time T4, which exceeds the threshold level SH of the inverter 62, the inverters 62 and 63 are sequentially turned on,
The clock CK and the inverted clock CK bar are output, and the flip-flops 20, 22, 24,... And the flip-flops 40, 42, 44,.

At this time, by setting the threshold level of the inverter 62 to be higher, a sharper rising edge of the waveform can be obtained in the period from the time T3 'to the time T4. A slight variation in the length of the signal line 50 is absorbed. As a result, in the example of FIG.
K20, inverted clock CK20 bar, clock CK4
0 and the inverted clock CK40 bar rise or fall at the same timing, as is apparent from each flip-flop 20, 2
2, 24 ... and flip-flops 40, 42, 44 ...
Can be operated at the same timing.

[0023]

As described above, according to the present invention, the present invention has a first driving means for driving a clock signal and a high-level threshold connected to the output side of the first driving means. A plurality of flip-flops having a second driving unit and a dedicated wire terminal connected to an output side of the first driving unit, and operating in synchronization with an output of the second driving unit; Since each of the flip-flops is wired through each of the wired dedicated terminals , clock skew can be further improved, and the pattern layout process at the time of design is greatly simplified.

[Brief description of the drawings]

FIG. 1 is a schematic circuit diagram showing one embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a clock supply unit of the flip-flop of the semiconductor integrated circuit shown in FIG.

3A is an example of a time chart for explaining a clock supply operation of the semiconductor integrated circuit shown in FIG. 1, and FIG. 3B is a partially enlarged view thereof.

FIG. 4 is a diagram showing an outline of a conventional clock supply method for a semiconductor integrated circuit.

[Explanation of symbols]

20, 22, 24 ..., 40, 42, 44 ... flip-flop 50 signal line 61, 62, 63 inverter CW wired dedicated terminal CKN clock terminal CK clock CK bar inverted clock

Claims (2)

(57) [Claims] A first driving means for driving a clock signal; a second driving means having a high-level threshold connected to an output side of the first driving means; and a wired dedicated terminal connected to the output side, a semiconductor integrated circuit having a plurality of flip-flop which operates in synchronization with the output of the second driving means, wherein each flip-flop, respectively Only for the above wired
A semiconductor integrated circuit, wherein the semiconductor integrated circuit is wired via terminals . (2) The wire realizing a wired connection function
The dedicated terminal is connected to the flip-flop at the manufacturing stage.
Claims that are built into the part from the beginning
2. The semiconductor integrated circuit according to 1.