JPH09191052A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can improve the timing a clock signal, can be made small in structure and can reduce the wiring capacitance of clock signal wiring lines. SOLUTION: A clock buffer 3 is provided outside a random logic section 2 having a plurality of rows 1 of standard cells arranged as regularly spaced by a predetermined distance. Clock signal wiring lines are connected between the rows 1 of standard cells at intervals of every other row, and a clock signal to be transmitted through the clock signal wiring lines is supplied to predetermined cells in the adjacent two rows 1 having the clock signal wiring lines provided therebetween.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI in which standard cells are layout-designed by automatic placement and routing.
The present invention relates to a semiconductor integrated circuit having improved clock signal wiring.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have become large-scaled and highly integrated, and the layout design has increased from manual design to automatic layout wiring. The automatic placement and routing is usually performed by the following procedure.

First, as shown in FIG. 3, logic cells (NA
A block (hereinafter referred to as a row) 11 in which standard cells such as ND, NOR), an inverter (IV), and a flip-flop (FF) are arranged in the lateral direction is created to realize a desired logic. . Next, as shown in FIG. 4, a plurality of rows 11 are arranged in the vertical direction at predetermined intervals to realize a desired logic. Next, as shown in FIG. 5, cells in the same row 11 are wired by the wiring a and cells between different rows 11 are wired by the wiring b or the row 11
Wiring is performed by the wiring c that passes through the cell. Such a layout design is automatically performed unless otherwise specified.

In the semiconductor integrated circuit layout-designed in this way, in the case of the synchronous system which is synchronized with the clock signal, as shown in FIG. A clock buffer 13 for generating a clock signal supplied to a standard cell such as a latch or a flip-flop in the random logic 12 may be arranged outside the. The clock buffer 13 generates a clock signal supplied to the standard cell according to a clock signal (CLK) supplied from the outside.

In such a configuration, the clock signal generated by the clock buffer 13 is supplied to the standard cell of a predetermined row 11 via the clock signal wiring CLK_DA. This clock signal wiring CLK_DA
When the automatic placement and routing is performed automatically, the layout is designed as shown in FIG. 6, for example.

In the clock signal wiring CLK_DA laid out in this way, the original operation timing of the circuit and the clock skew are not considered at all. For this reason,
Normally, when performing automatic placement and routing, the clock signal wiring is routed only between the rows 11 in the random logic 12,
The wiring inside the row 11 and the wiring passing through the row 11 are prohibited. FIG. 7 shows an example of a layout design in which automatic placement and wiring are performed in this way.

In such automatic placement and routing, for the cells A and B placed adjacent to the same row 11, for example, as shown in FIG. The clock signal is supplied via the clock signal wiring a, and the clock buffer 13 is provided in the cell B.
There is a case where the layout design is performed so that the clock signal output from the device is supplied via the clock signal wiring b.

In such a clock signal wiring layout, although the cell A and the cell B are adjacent to each other, the wiring length of the clock signal wiring a from the clock buffer 13 to the cell A is equal to that of the clock buffer 13. Since it is longer than the wiring length of the clock signal wiring b to the cell B, there is a skew between the clock signal supplied to the cell A and the clock signal supplied to the cell B, which cannot be ignored in the operation of the circuit. However, there is a possibility that a timing difference may occur between the clock signals, resulting in a malfunction.

Further, since the clock signal wiring is formed between all the rows 11, the vertical distance of the random logic portion 12 becomes long and the layout area is increased. Especially when the number of rows 11 is large (100 or more),
Not only will the layout area be increased, but also the wiring capacitance of the clock signal wiring will be increased, which will cause a delay of the clock signal.

[0010]

As described above,
In a conventional semiconductor integrated circuit in which a row including a standard cell that uses a clock signal is layout-designed by automatic placement and routing, a clock signal wiring for supplying a clock signal to a predetermined standard cell is formed between all rows. Since the configuration is adopted, skew occurs in the clock signal and the timing of the clock shifts,
There was a risk of malfunction.

Further, since the clock signal wiring is formed between all the rows in the random logic part,
The layout area of the random logic is increased, and the size of the configuration is increased. Further, the total wiring length of the clock signal wiring has become longer with the increase in the scale of the row, and the wiring capacitance has been increased.

Therefore, the present invention has been made in view of the above, and an object thereof is to provide a semiconductor integrated circuit in which a row including a standard cell using a clock signal is layout-designed by automatic placement and wiring, It is an object of the present invention to provide a semiconductor integrated circuit capable of improving the timing of a clock signal, reducing the size of the configuration, and reducing the wiring capacity of the clock signal wiring.

[0013]

In order to achieve the above object, according to the present invention, a row of a standard cell group in which a plurality of standard cells are arranged in a horizontal direction is arranged in a vertical direction at a predetermined interval. And a random logic region formed and arranged outside the random logic region,
A clock buffer circuit that generates a clock signal to be supplied to the standard cell, and clock signal lines that transmit the clock signal output from the clock buffer circuit to the standard cell are formed every other row between the rows. The clock signal transmitted through the clock signal wirings formed every other row between the rows is supplied to predetermined standard cells of two adjacent rows sandwiching the clock signal wiring.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the invention described in claim 1.

In FIG. 1, the semiconductor integrated circuit has a random logic section 2 in which a plurality of standard cells are arranged in the horizontal direction by a automatic layout wiring and a plurality of rows 1 are arranged in the vertical direction at predetermined intervals. And a clock buffer 3 arranged and formed outside the random logic unit 2 to generate a clock signal supplied to the standard cell based on a clock signal (CLK) given from the outside. In the above, clock signal wiring CLK_DA for transmitting the clock signal output from the clock buffer 3 to the standard cell
Are formed every other row 1, and the clock signals transmitted through the clock signal wirings formed every other row 1 are stored in predetermined rows of two rows 1 adjacent to each other with the clock signal wiring interposed therebetween. It is configured by being supplied to a standard cell.
That is, the clock signal wiring in the random logic part 2 is formed by dividing one row into two adjacent rows 1 with the clock signal wiring interposed therebetween, which is reduced to half compared with the conventional configuration shown in FIG.

In such a configuration, when the layout design is performed by the automatic placement and routing, for example, as shown in FIG. 2, for the standard cells C and the standard cells D adjacently arranged in the same row 1, Then, the layout of the clock signal wirings is designed such that the clock signals output from the clock buffer 2 are supplied via the same clock signal wiring c. Therefore, the skew of the clock signal supplied to the cells arranged adjacent to each other is significantly reduced as compared with the conventional case, the clock timing deviation becomes negligible in the operation of the circuit, and the malfunction does not occur.

In addition, since every other region in which the clock signal wiring is not formed occurs in the region between the row 1, that is, in the region between the row 1, the region where the clock signal wiring is formed and the region where the clock signal wiring is not formed alternate. Occurs in the low 1
The layout area of the area where the clock signal wiring is not formed is smaller than the conventional one, and the random logic unit 2
The vertical length of can be reduced by about 25% compared to the conventional one.

Further, since the total wiring length of the clock signal wiring is reduced by about 50%, the wiring capacity can be reduced by about 50%. Such an effect becomes remarkable as the number of rows 1 increases, which is an extremely advantageous effect as compared with the conventional one.

[0020]

As described above, according to the present invention, every other clock signal wiring is formed between the rows, and the clock signals transmitted through the clock signal wiring are adjacent to each other with the clock signal wiring interposed therebetween. Since it is supplied to the predetermined standard cells in one row, the timing deviation of the clock signal is suppressed, and the malfunction can be prevented.

Further, the layout area can be reduced and the wiring capacity of the clock signal can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the invention as set forth in claim 1;

FIG. 2 is a diagram showing a wiring example of a clock signal wiring in the configuration shown in FIG.

FIG. 3 is a diagram showing a configuration of a row in which standard cells are arranged.

FIG. 4 is a diagram showing a configuration of a random logic unit in which the rows shown in FIG. 3 are arranged.

FIG. 5 is a diagram showing an example of wiring between rows.

FIG. 6 is a diagram showing a layout of a random logic part and a clock signal wiring.

FIG. 7 is a diagram showing another layout of the random logic unit and the clock signal wiring.

FIG. 8 is a diagram showing a wiring example of clock signal wirings for adjacent standard cells.

[Explanation of symbols]

 1, 11 row 2, 12 random logic part 3, 13 clock buffer a, b, c, CLK_DA clock signal wiring

Claims (1)

[Claims] 1. A random logic region in which a plurality of rows of standard cells, each of which is formed by arranging a plurality of standard cells in a horizontal direction, are arranged in a vertical direction at a predetermined interval, and arranged and formed outside the random logic region. A clock signal circuit for generating a clock signal to be supplied to the standard cell, and one clock signal line for transmitting the clock signal output from the clock buffer circuit to the standard cell is provided between the rows. A clock signal which is formed every other row and which is transmitted through every other clock signal wiring formed between the rows is supplied to a predetermined standard cell of two adjacent rows sandwiching the clock signal wiring. And a semiconductor integrated circuit.