JPH0369163A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of stages of a clock driver, to reduce wiring parasitic resistance and to reduce clock skew by providing in advance a basic cell with at least one wiring inside a clock signal cell whose signal wiring is wider than that of usual one. CONSTITUTION:In a semiconductor integrated circuit device including a primitive function block which is formed by connecting a plurality of basic cells mutually by a signal wiring, at least one wiring 7 inside a clock signal cell whose signal wiring is wider than that of usual one is arranged in advance. For example, a basic cell is formed by first type diffusion regions 1a to 1c, second type diffusion regions 2a to 2c, a polysilicon gate electrode 3a, 3b, gate connecting regions 4a1, 4a2, 4b1, 4b2, a wiring 5 inside a first power source cell, a wiring 6 inside a second power source cell, and the wiring 7 inside a clock signal cell whose wire is wide enough to enable connection of a number of flip flops when compared with a conventional one.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a primitive function block of a channel type and channelless type gate array, or a standard cell type semiconductor integrated circuit device. The present invention relates to a basic cell constituting a basic cell, and particularly to a basic cell configuration for reducing clock skew.

[Conventional technology]

FIG. 4 shows an example of a basic cell configuration of a semiconductor integrated circuit device using a CMOS process according to the prior art.

Conventionally, in general, first diffusion regions (for example, P-type diffusion layer regions) la, . . . , second diffusion regions (for example, N-type diffusion layer regions) 2a, . 3a, 3b, and gate connection regions 4al, 4a2,
4bl, 4b2, the gate polysilicon electrode 4, and the first
In the prior art, the wiring in the power supply cell (for example, VDD power supply, 5V) 5 and the second power supply cell wiring (for example, VSS power supply, 0■, ground potential) 6, etc. By using one or more basic cells and interconnecting them with normal signal wiring with line widths that are referenced in the application process,
Primitive function blocks, which are dozens to hundreds of basic functional blocks, were constructed.

These primitive function blocks and RAM, ROM.

A single semiconductor integrated circuit device was realized by interconnecting the I10 buffers and the like with signal wiring having a normal line width. FIG. 5 shows an example of clock distribution wiring using a conventional basic cell. In the basic cell of the conventional technology, wiring 5 with the same line width as a normal signal line is used as wiring for clock distribution.
5, 56, 57° 58.59, the current capacity that can flow through the line width is determined by electromigration and wiring parasitic resistance, and as a result, the clock drivers 51, 52, 53, 54 The number of flip-flops that can be driven by (the so-called fan-out number)
is restricted. Therefore, the clock signal input from the clock terminal CLK is transmitted to the clock driver 5 of the first stage.
1, the second stage clock driver 52.53.
.
0, the clock driver 53 distributes the clock signal to the second group of flip-flops 11 whose number is less than or equal to the fan-out limit number, and the clock driver 54 distributes the clock signal to the N-th flip-flops 11 whose number is less than or equal to the fan-out limit number. N
The clock signal is distributed to the seven lip-flops 12 in groups of 3.4, 5°, . . . n, a natural number. Fifth
The figure shows an example with two stages of clock drivers, but in a logic circuit with hundreds to thousands of flip-flops,
The clock driver has about 5 to 7 stages.

[Problem to be solved by the invention]

The basic cell configuration of the conventional semiconductor integrated circuit device described above is shown in FIG. 5 because there is no special consideration regarding the wiring for clock signal distribution, and the wiring is similar to normal signal wiring. Similarly, the clock driver for clock signal distribution has several stages, and the wire lengths of the wiring lines 56, 57, and 58 vary depending on the number of flip-flops and the layout position. , there is a drawback that there is large variation in the arrival time of the clock signal to each flip-flop, that is, there is a large clock skew.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a primitive function block configured by interconnecting a plurality of basic cells with signal wiring, in which the basic cell has a line width larger than that of the normal signal wiring. At least one large clock signal cell-like wiring is arranged in advance.

〔Example〕

FIG. 1 is a layout diagram of a basic cell in a first embodiment of the present invention, showing the basic cell configuration in the case of CMOS technology.

la, lb, lc are diffusion regions of the first type (e.g. P
type diffusion layer regions), 2a, 2b, 2c are second type diffusion regions (for example, N type diffusion layer regions), 3a,
3b is a polysilicon gate electrode, 4a'l, 4a2, 4
bl, 4b2 are gate connection regions, 5 is the wiring in the first power cell (e.g. VDD power, 5V), 6 is the wiring in the second power cell (e.g. vSS power, 0■, ground potential), 7 is the basic cell in advance This is a clock signal cell-like wiring provided in the circuit, and its line width is thick enough to connect many flip-flops compared to the line width of normal signal wiring.

The aim is to strengthen electromigration resistance and reduce wiring parasitic resistance.

FIG. 3 is a block diagram showing how clock signals are distributed in a semiconductor integrated circuit device using a basic cell according to the present invention. A clock signal input from the clock signal terminal CLK is input to the clock driver 31. The clock driver 31 is designed to be able to sufficiently drive many flips 70 at high speed. The clock signal wiring 32 shown in bold lines interconnects sufficiently large clock signal cell-like wiring provided in the basic cell, so in this example, the clock signal wiring branch 33 of each flip-flop connects all the flip-flops. Fluoruffs 10 to 12 can be driven simultaneously. That is, only one stage of the clock driver is required, and all the flip-flops are driven by -1 clock signal wiring, so that clock skew can be significantly reduced.

Although the example here shows an example of a basic cell in CMOS technology, it goes without saying that the present invention can also be applied to B1CMOS technology.

FIG. 2 is a layout diagram of a basic cell in a second embodiment of the invention, showing the basic cell configuration in the case of CMOS technology.

Reference numeral 8 represents a first clock signal cell wiring, and 9 represents a second glue p work signal cell wiring. 8 and 9 are provided in advance in the basic cell as in the first embodiment, and the line width thereof is sufficiently thick so that many flip-flops (flimitive function blocks) can be connected. In contrast to the first embodiment, the second embodiment has two clock signal cell-like wirings, taking into account multiphase cross signals, and changes the position of each clock signal cell-like wiring to a gate. What is done between the connection area and the wiring within the power supply cell is different, but since they are basically the same, detailed explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention reduces the number of stages of clock drivers and reduces wiring parasitic resistance by providing a basic cell of a semiconductor integrated circuit with a clock signal cell-like wiring whose line width is significantly larger than that of a normal signal wiring. This has the effect of realizing a semiconductor integrated circuit device with significantly reduced clock skew.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of a basic cell in a first embodiment of the present invention, FIG. 2 is a layout diagram of a basic cell in a second embodiment, and FIG. 3 is a diagram of clock signal distribution in a semiconductor integrated circuit device of the present invention. FIG. 4 is a block diagram showing the basic cell layout in the conventional example, and FIG. 5 is a block diagram showing the state of clock signal distribution in the conventional example. la, lb, lc...first type diffusion region, 2a, 2b, 2c...second type diffusion region, 3a, 3b...polysilicon gate electrode,
4a1゜4a2, 4bl, 4b2--gate connection region,
5... Wiring in the first power supply cell, 6... Wiring in the second power supply cell, 7... Wiring in the clock signal cell, 8... First clock signal cell wiring,
9...Second clock signal cell wiring, 10.
...First group of flip-flops, 11.
...Second group of flip-flops, 12.
...Nth group of flip-flops, 31.
... Clock driver 32 ... Significant clock signal wiring, 33 ... Clock signal wiring branch, 51, 52, 53.54 ... Clock driver 55.56, 57.58...Clock signal wiring, 59...Clock signal wiring branch, CL
K...Clock input terminal.

Claims (1)

[Claims] In a semiconductor integrated circuit device including a primitive function block configured by interconnecting a plurality of basic cells with signal wiring, the basic cell has at least a clock signal cell internal wiring whose line width is larger than a normal signal wiring. A semiconductor integrated circuit device characterized in that one wire is arranged in advance.