JPH06231594A - Data transfer circuit - Google Patents

Abstract

PURPOSE:To obtain a data transfer circuit capable of being operated by a single clock. CONSTITUTION:A first transistor 1, into which a data signal 10a from the outside is input, a first inverting circuit 20 logically inverting an output from said first transistor, and a second inverting circuit 21 logically inverting a data signal output from the first inverting circuit 20 and feeding back the logically inverted data signal to the input side of the first inverting circuit 20 are mounted. A second transistor 2 connected between the output side of the second inverting circuit 21 and the input side of the first inverting circuit 20, supplied with a cock signal 9a in common with the first transistor 1 and complementally operated with the first transistor 1 is set up, and the first and second transistors 1, 2 are operated only by the clock signal 9a, and the data signal 10a is transferred successively.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data transfer circuit.

[0002]

As is well known, a data transfer circuit has been conventionally used as a circuit for transferring an input data signal. The conventional data transfer circuit includes a first transistor 3 to which a signal from the outside is given as shown in FIG.
A data transfer circuit is used in which 1 is connected to a second transistor 32 to which a signal output from the first transistor 31 is given.

In order to operate the data transfer circuit configured as described above, complementary clock signals CL1 and CL2 as shown in FIG. 4 are supplied to the first transistor 31 and the second transistor 32, respectively. There is a need to.

[0004]

As described above, the conventional data transfer circuit includes the first transistor 31 and the second transistor 31.
Clock signal CL with different phase in the transistor 32 of
It could not be operated without supplying 1 and CL2 respectively. As described above, in order to supply a plurality of clock signals, it is necessary to provide the clock signal wiring and the clock signal input terminal. Therefore, the conventional data transfer circuit has a limit in reducing the area required for installation. there were.

In view of the above problems, it is an object of the present invention to provide a data transfer circuit which can be operated with a single clock.

[0006]

A data transfer circuit according to the present invention comprises a first transistor to which a signal from the outside is input, a first inverting circuit for logically inverting the output of the first transistor, and the above-mentioned first inverting circuit. A second inverting circuit that is connected in parallel with the first inverting circuit and logically inverts a data signal output from the first inverting circuit to feed back to the input side of the first inverting circuit; A clock signal that is connected between the output side of the second inverting circuit and the input side of the first inverting circuit and is common to the first transistor, and is complementary to the first transistor. A data transfer circuit having a second transistor which operates.

[0007]

Since the data transfer circuit of the present invention has the above technical means, if the above-mentioned data transfer circuits are connected in series, the input signal of each data transfer circuit is connected to the next stage for every cycle of the clock signal. Since they are successively transferred to the data transfer circuit, the input data signal can be operated with a single clock signal.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the data transfer circuit of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the data transfer circuit of the present invention, in which four stages of data transfer circuits are connected.

In FIG. 1, 1, 4, 5, 8 are N-type transistors, 2, 3, 6, 7 are P-type transistors, 9 is a clock terminal, 10 is a signal input terminal, 14 is a signal output terminal, 11, Reference numerals 12 and 13 are internal signal paths. Also, 2
Reference numerals 0 to 27 are inverting circuits, 20, 22, 24 and 26 are first inverting circuits, and 21, 23, 25 and 27 are second inverting circuits.

FIG. 2 is an operation waveform diagram showing a signal transfer state in the data transfer circuit of this embodiment. As is apparent from FIG. 2, the data signal 10a input from the signal input terminal 10 is sequentially transferred by the following operation.

That is, when the clock signal 9a input from the clock terminal 9 is "H", the N-type transistors 1, 4, 5 and 8 operate. Next, when the P-type transistors 2, 3, 6, and 7 operate when the clock signal 9a is "L", the data signal 1 input from the signal input terminal 10 is input.
0a is transferred to the internal signal path 12. By repeating such an operation, the input data signal 10a transferred to the internal signal path 12 is transferred to the signal output terminal 14.

In this way, the data transfer circuit of the present embodiment uses the single clock signal 9a to input data signal 1
0a can be transferred one after another. Therefore, unlike the conventional data transfer circuit, it is not necessary to provide a plurality of clock signal wirings or a plurality of clock signal input terminals for supplying a plurality of clock signals, and a circuit necessary for installing the data transfer circuit. The area can be reduced.

[0013]

As described above, according to the present invention, since the data transfer circuit of the present invention can be operated by a single clock signal, the clock signal wiring and the clock signal necessary for performing the data transfer operation can be obtained. The number of input terminals can be reduced, and the circuit area required for installing the data transfer circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a data transfer circuit showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a transfer state of a data signal in the transfer circuit shown in FIG.

FIG. 3 is a circuit diagram showing an example of a conventional data transfer circuit.

FIG. 4 is a waveform diagram for explaining the operation of the data transfer circuit shown in FIG.

[Explanation of symbols]

1, 4, 5, 8 N-type transistor 2, 3, 6, 7 P-type transistor 9 Clock terminal 9a Clock signal 10 Signal input terminal 10a Data signal 14 Signal output terminal 11, 12, 13, 14 Internal signal path 20, 21 , 22, 23, 24, 25, 26, 27 Inversion circuit

Claims (1)

[Claims] 1. A first transistor to which a signal from the outside is input, a first inverting circuit for logically inverting the output of the first transistor, and a first inverting circuit connected in parallel with the first inverting circuit. , Above first
A second inverting circuit that logically inverts a data signal output from the inverting circuit and feeds it back to the input side of the first inverting circuit; and an output side of the second inverting circuit and the first inverting circuit. A data transfer, comprising: a second transistor connected between the input side and the first transistor, the clock signal being supplied in common with the first transistor, and the second transistor operating complementarily to the first transistor. circuit.