JPS631069A - Manufacture of field-effect semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a field-effect semiconductor device with a shallow junction by forming a gate electrode, a top surface and a side surface of which are surrounded by an insulating film, shaping a single crystal or polycrystalline semiconductor film onto a residual semiconductor surface and implanting ions through the semiconductor film to form source and drain regions. CONSTITUTION:A field insulating film 2 is shaped to a p-type Si semiconductor substrate 1, using an Si3N4 film as a mask. The Si3N4 film is removed, the surface of an active region surrounded by the insulating film 2 is exposed, and an insulating film is formed through thermal oxidation. A polycrystalline Si film containing an impurity and an insulating film are shaped onto the insulating film. Three layers consisting of the insulating film-the polycrystalline Si film-the insulating film are patterned, and an insulating film 5 on the top surface of a gate electrode, a polycrystalline Si gate electrode 4 and a gate insulating film 3 are shaped. An SiO2 insulating film 6 is formed, and the film 6 is removed, leaving only the side surface of the gate electrode through an RIE method. An Si film 7 is shaped to the surface of the active region, and As ions are implanted, thus forming n<+> type source region 8 and drain region 9.

Description

Detailed Description of the Invention [Summary] The present invention provides a method for manufacturing a field effect semiconductor device, in which a gate electrode whose top and side surfaces are surrounded by an insulating film is formed in an active region, and the remaining part of the active region is By forming a single-crystalline or polycrystalline semiconductor film on the exposed portion, and forming a source region and a drain region by implanting ions through the single-crystalline or polycrystalline semiconductor film, these source and drain regions can be gated. This makes it possible to significantly reduce the thickness of the region and to lower the resistance of the source and drain regions, making it easier to increase the degree of integration of field effect semiconductor devices and solving difficulties in the manufacturing process. It is something.

[Industrial application field]

The present invention relates to improvements in methods for manufacturing field effect semiconductor devices having shallow junctions.

[Conventional technology]

FIG. 6 shows a cutaway side view of the main part of the field effect semiconductor device in the middle of the manufacturing process.

In the figure, 11 is a p-type silicon semiconductor substrate, 12 is a field insulating film made of silicon dioxide (SiOz),
Reference numeral 13 indicates a gate insulating film made of 5i02, 14 a polycrystalline silicon gate electrode, 15 an n+ type source region, and 16 an n+ type drain region.

To manufacture this field effect semiconductor device, a semiconductor substrate 1
1, a field insulating film 12 is formed by applying a selective oxidation method (for example, Locos method) using a silicon nitride (Si3N4) film or the like as a mask, and then the Si3N4 film used as a mask is removed to remove the field insulating film 12. The gate insulating film 13 and the polycrystalline silicon gate electrode are formed by exposing the surface of the active region surrounded by the insulating film 12, and then forming a thin insulating film and a polycrystalline silicon film and then patterning them. 14, and then by using the ion implantation method using the polycrystalline silicon gate electrode 14 as a mask, n is formed by a so-called self-alignment method.
++ source region 15 and n'' type drain region 16 are formed.

This technique of forming source and drain regions using a self-alignment method using the gate electrode as a mask is effective for high integration because it can eliminate difficulties in aligning these regions. Therefore, it has been widely used.

Incidentally, in recent years, in field effect semiconductor devices, it has become necessary to reduce the gate electrode length to 1 [μm] or less.

If the manufacturing process described with reference to FIG. 6 is adopted, the depth of the source region 15 and drain region 16 will be, for example, 0.3 to 0.4 [μ] no matter how shallow the efforts are made.
Therefore, the width of the gate electrode becomes approximately 1 [m], and as a result, the gate electrode length becomes approximately 1 [m].
μm] or sub-micron, it is no longer possible to
Such techniques cannot be applied.

Therefore, attempts are currently being made to reduce the lateral spread of the source and drain regions by forming them shallowly, thereby achieving higher integration and higher speed.

FIG. 7 shows a cutaway side view of the main parts of a field effect semiconductor device in the middle of the manufacturing process to explain the conventional technique of forming shallow junctions, and the same symbols as those used in FIG. 6 refer to the same parts. or have the same meaning.

In the figure, 17 is an insulating film on the top surface of the gate electrode made of SiO2, 18 and 19 are insulating films on the side surfaces of the gate electrode made of Si02, 20 is a polycrystalline silicon film, and 20A
2A and 2B respectively indicate grooves for dividing the polycrystalline silicon film 20.

When manufacturing this field effect semiconductor device, after forming the field insulating film 12, an Si 3 film used as a mask is used.
The process until the N 4 film is removed to expose the surface of the active region is the same as the conventional technique described with reference to FIG. Next, by patterning them, a gate insulating film 13 and a polycrystalline silicon gate electrode 1 are formed.
4. Form an insulating film 17 on the top surface of the gate electrode, then form insulating films 18 and 19 on the side surfaces of the gate electrode, and then
An impurity-containing polycrystalline silicon IIu 20 is formed, and then heat treatment is performed to form an n++ source region 15 and an n1 type drain region 16 by so-called solid-phase diffusion, and then an impurity-containing polycrystalline silicon film 20 is formed. The source and drain are separated by buttering.

The n++ source region 15 and n+
The depth of the mold drain region 16 is 0.1 to 0.2 [μm
], the horizontal spread is extremely reduced, which is effective for high integration.

[Problems to be Solved by the Invention] According to the prior art described with reference to FIG. 7, the junction obtained by forming the source region and the drain region can be made quite shallow as described above. A dividing groove 2OA must be formed in the polycrystalline silicon film 20 used as a diffusion source to insulate and separate the source and drain.

However, as mentioned above, currently the gate electrode is 1 [
μm] or less, it is not easy to align the dividing groove 2OA in the vicinity of the top of the gate electrode.
The manufacturing method described with reference to the figures becomes more difficult to implement as semiconductor devices become more highly integrated.

When manufacturing this type of field effect semiconductor device, the present invention makes it possible to easily manufacture a field effect semiconductor device having a shallow junction by appropriately combining conventionally known techniques.

Means for Solving Problem C] According to the method for manufacturing a field effect semiconductor device according to the present invention,
surrounded by a field insulating film (for example, field insulating film 2) and made of a single crystal semiconductor (for example, p-type silicon semiconductor substrate 1).
) Active with exposed surfaces? The top and side surfaces are insulated 1t in the i1 area! i! <For example, a gate electrode surrounded by an insulating film 5 and 6) (for example, a polycrystalline silicon gate electrode 4)
Next, a selective growth method is applied to form a single crystal or polycrystalline semiconductor film (for example, a silicon film) on the remaining portion of the single crystal semiconductor surface, and then an ion implantation method is applied. The method includes a step of forming a source region (for example, an n++ source region 8) and a drain region (for example, an n+ type drain region 9) on the surface of the active region through the single crystal or polycrystalline semiconductor film.

[Effect]

By adopting the above method, it is possible to form the source region and the drain region to be significantly shallower than in the case of applying the conventional technology, so that the lateral spread of these regions is also extremely reduced, making it possible to improve the field effect semiconductor device. It is very effective in increasing the degree of integration of transistors, and at the same time, it is possible to lower the resistance of the source and drain regions, so it is possible to miniaturize the transistor while maintaining its performance. Since the silicon film used in this process is automatically separated from the beginning, there is no need for microfabrication to separate the source and drain, and therefore, the present invention is extremely easy to implement.

〔Example〕

1 to 5 are cross-sectional side views of essential parts of a field effect semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

See Figure 1 (1) Si 3 N 4 on p-type silicon semiconductor substrate 1
A selective oxidation method using the film as a mask is applied to reduce the thickness, for example, to 0.
A field insulating film 2 having a thickness of 6 [μm] is formed.

(2) After removing the Si 3 N 4 film used as a mask and exposing the surface of the active region surrounded by the insulating film 2, a thermal oxidation method is applied to form a film with a thickness of, for example, 300 mm. ! Forms the lamina.

(3) Chemical vapor deposition (chemica I vap).

An impurity-containing polycrystalline silicon film having a thickness of, for example, 3,000 to 4,000 μm is formed by applying a CVD method. In order to form this impurity-containing polycrystalline silicon film, first, a polycrystalline silicon film is formed, and then impurities are thermally diffused or
Alternatively, impurity ions may be implanted and heat treated.

(4) By applying a thermal oxidation method, an insulating film with a thickness of, for example, 3,000 mm is formed on the surface of the polycrystalline silicon film.This insulating film can also be formed by applying a CVD method. can.

(5) By applying ordinary photolithography technology, the three layers formed in steps (2) to (4) above, consisting of the insulating film - polycrystalline silicon film - insulating film, are patterned, and the gate An insulation 1 pattern 5 on the top surface of the electrode, a polycrystalline silicon gate electrode 4, and a gate insulating film 3 are obtained. Note that the material for forming the gate electrode 4 is not limited to the above-mentioned polycrystalline silicon, but also tungsten silicide (WSi), molybdenum silicide (MO3i), etc.
, titanium silicide (TiSi), etc. can be arbitrarily selected.

By applying the f61cVD method (see Fig. 2), a thickness of, for example, 20
An insulating film 6 made of 5i02 of about 00 to 3000 (person) is formed.This insulating film 6 is made of Si 3 N
4 film or SiC2 film and Si3N 4 Jl! It may also be a composite film with J.

See Figure 3. (7) Reactive ion etching using CF4+T2 as the etching gas.
By applying the etching (RIE) method, the insulating film 6 formed in step (6) is anisotropically etched, leaving only the side surfaces of the gate electrode and removing the rest. Incidentally, when the insulating film 6 is a Si 3 N 4 film, it is preferable to use CF4+NZ as the etching gas.

Refer to FIG. 4 (8) A silicon film 7 having a thickness of, for example, 0.2 to 0.3 μm is formed on the surface of the exposed active region by selective epitaxial growth.

The following conditions are used to carry out the selective epitaxial growth method.

Technology: Low pressure CVD method Reactant gas: 5iHCj! 3 (0,5~1.0 (f
/min]) H2 (5-6 [l/min]) Temperature: 900-1000 ('C) Pressure crab 0. 1 to 10 (Torr) Note that although the silicon film 7 is made of single crystal here, it can be replaced with a polycrystalline silicon film.

Refer to FIG. 5 (9) As ions are implanted using the ion implantation method.

Examples of conditions for this ion implantation are as follows.

Dose: l X l O"(C111-") Acceleration energy = 60 to 70 [KeV] 00 In order to activate the ion-implanted As, heat treatment is performed at a temperature of 1000 ("C) and a time of 30 [minutes], for example. I do.

As a result, the depth from the gate region is approximately 0°1 [μm
] n++ source region 8 and n+ drain region 9 are formed.

0υ After this, a protective film and electrodes are formed and completed using normal techniques.

The depth of the source region 8 and drain region 9 in the field effect semiconductor device obtained in this way is 0.0 mm as described above. I Cμm], so their lateral spread is also about that extent. It goes without saying that if an n-type silicon semiconductor substrate is used and the source and drain regions are p+ type, a p-channel field effect semiconductor device can be obtained by the same process.

〔Effect of the invention〕

In the method for manufacturing a field effect semiconductor device according to the present invention, a gate electrode whose top and side surfaces are surrounded by an insulating film is formed in the active region, and a single crystal or polycrystalline film is formed in the remaining part of the active region. A semiconductor film is formed, and ions are implanted through the single crystal or polycrystalline semiconductor film to form a source region and a drain region.

By adopting the above structure, it is possible to form the source region and the drain region significantly shallower than in the case where the conventional technology is applied, so the lateral spread of these regions is also greatly reduced, and the electric field effect can be reduced. It is very effective in increasing the integration of semiconductor devices, and at the same time, it is possible to reduce the resistance of the source and drain regions, so it is possible to miniaturize the transistor while maintaining its performance.
Since the silicon film used for ion implantation of impurities is automatically separated from the beginning, there is no need for microfabrication to separate the source and drain, and therefore the present invention is extremely easy to implement. It is.

[Brief explanation of drawings]

1 to 5 are cutaway side views of essential parts of a field effect semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS. 6 and 7 are midway through the process according to the prior art. 2A and 2B are cross-sectional side views of essential parts of a field-effect semiconductor device, respectively. In the figure, l is a p-type silicon half-gate body substrate, 2 is a field insulating film, 3 is a gate insulating film, and 4 is a polycrystalline silicon substrate.
The gate electrode, 5 is an insulating film on the top surface of the gate electrode, 6 is an insulating film on the side surface of the gate electrode, 7 is a silicon film, 8 is an n++ source region, and 9 is an n+ type drain region. Figure 3 Figure 4 Cutaway side view of main parts of conventional example Figure 6

Claims (1)

[Claims] A step of forming a gate electrode whose top and side surfaces are surrounded by an insulating film in an active region surrounded by a field insulating film and with a single crystal semiconductor surface exposed, and then a selective growth method. forming a single-crystalline or polycrystalline semiconductor film on the remaining portion of the single-crystalline semiconductor surface by applying ion implantation to the surface of the active region through the single-crystalline or polycrystalline semiconductor film; 1. A method of manufacturing a field effect semiconductor device, the method comprising the step of forming a region and a drain region.