JPS63106219U - - Google Patents
Info
- Publication number
- JPS63106219U JPS63106219U JP20376086U JP20376086U JPS63106219U JP S63106219 U JPS63106219 U JP S63106219U JP 20376086 U JP20376086 U JP 20376086U JP 20376086 U JP20376086 U JP 20376086U JP S63106219 U JPS63106219 U JP S63106219U
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor device
- input terminal
- delay circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Manipulation Of Pulses (AREA)
Description
第１図は本考案の説明図、第２図および第３図
は本考案の具体例を示す回路図、第４図はノイズ
パルスの説明図である。
図面で１０はアンドゲート、Ｔは入力端、１２
，１４，……は遅延回路を構成するインバータで
ある。
FIG. 1 is an explanatory diagram of the present invention, FIGS. 2 and 3 are circuit diagrams showing specific examples of the present invention, and FIG. 4 is an explanatory diagram of a noise pulse. In the drawing, 10 is an AND gate, T is an input terminal, 12
, 14, . . . are inverters forming a delay circuit.
Claims (1)
の一方の入力端に与えられる入力信号を遅延させ
て該ゲートの他方の入力端に与える遅延回路とか
らなるノイズ除去回路を、チツプ上集積回路の信
号入力側に挿入してなることを特徴とする半導体
装置。 (2) 遅延回路は複数個のインバータにより構成
されることを特徴とする実用新案登録請求の範囲
第１項記載の半導体装置。[Claims for Utility Model Registration] (1) A noise removal circuit consisting of an AND gate or a NOR gate, and a delay circuit that delays an input signal applied to one input terminal of the gate and applies it to the other input terminal of the gate. What is claimed is: 1. A semiconductor device comprising: inserted into the signal input side of an integrated circuit on a chip. (2) The semiconductor device according to claim 1, wherein the delay circuit is comprised of a plurality of inverters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20376086U JPS63106219U (en) | 1986-12-25 | 1986-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20376086U JPS63106219U (en) | 1986-12-25 | 1986-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63106219U true JPS63106219U (en) | 1988-07-09 |
Family
ID=31169390
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20376086U Pending JPS63106219U (en) | 1986-12-25 | 1986-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63106219U (en) |
-
1986
- 1986-12-25 JP JP20376086U patent/JPS63106219U/ja active Pending
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